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Seven segment display and clock counter

Short answer

A seven-segment display uses seven LEDs (a–g) to show digits 0–9; types are common cathode, common anode, and static or multiplexed drive. The counter watch uses four multiplexed common-cathode digits (MM:SS) driven by an 8051: Timer 0 interrupts every 5 ms to refresh one digit via shared segment bus on P1 and NPN transistors on P3.0–P3.3; seconds and minutes increment in the ISR.

What is seven segment display and write its types. Design a circuit with 7 segments display which is used as a counter watch which display second and minute.

Seven-segment display

A seven-segment display is a package of seven LEDs (segments a-g, plus a decimal point) arranged in the shape of an 8, used to show the digits 0-9 and some letters.

    --a--
   f|   |b
    --g--
   e|   |c
    --d--  .dp

Types:

  1. Common cathode: all LED cathodes are joined and grounded; a segment lights when its pin is 1.
  2. Common anode: all anodes are joined to +5 V; a segment lights when its pin is 0.
  3. By drive method: static (one decoder/port per digit) and multiplexed (the digits share the segment lines and are turned on one at a time).

Design of a minutes:seconds counter

Use four common-cathode digits (MM:SS) with multiplexing, so only 7 + 4 port pins are needed.

              8051
  P1.0-P1.6 --[330R]--+--- a..g of all 4 digits (parallel)
  P3.0 -[1k]-NPN-- cathode, digit 0 (seconds units) -- GND
  P3.1 -[1k]-NPN-- cathode, digit 1 (seconds tens)  -- GND
  P3.2 -[1k]-NPN-- cathode, digit 2 (minutes units) -- GND
  P3.3 -[1k]-NPN-- cathode, digit 3 (minutes tens)  -- GND

Each NPN transistor (e.g. BC547) sinks the common-cathode current of one digit; a 1 on P3.x enables that digit. All digits share the segment bus on P1 and are shown one after another, each for 5 ms (so each digit is refreshed every 20 ms and looks steady).

Operation: Timer 0 interrupts every 5 ms. The interrupt routine puts the pattern of the next digit on P1 and enables that digit. After 200 interrupts (1 s) the seconds count is incremented; at 60 s it resets and the minutes are incremented; at 60 min both reset.

#include <reg51.h>

unsigned char code seg[10] = {0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F};
unsigned char sec = 0, min = 0;     /* time */
unsigned char idx = 0;              /* digit being refreshed */
unsigned int  ticks = 0;            /* 5 ms tick counter */

void timer0_isr(void) interrupt 1   /* Timer 0 overflow every 5 ms */
{
    unsigned char d;

    TH0 = 0xEC;  TL0 = 0x9C;        /* reload: 65536 - 5000 + 36 (ISR delay) = EC9CH */
    P3 = 0x00;                      /* blank all digits first */

    switch (idx) {                  /* pick the digit value */
        case 0:  d = sec % 10; break;
        case 1:  d = sec / 10; break;
        case 2:  d = min % 10; break;
        default: d = min / 10; break;
    }
    P1 = seg[d];                    /* segment pattern on Port 1 */
    P3 = 1 << idx;                  /* turn on one digit (P3.0 - P3.3) */
    idx = (idx + 1) & 3;            /* next digit, 0..3 */

    if (++ticks == 200) {           /* 200 x 5 ms = 1 s */
        ticks = 0;
        if (++sec == 60) {
            sec = 0;
            if (++min == 60) min = 0;
        }
    }
}

void main(void)
{
    TMOD = 0x01;                    /* Timer 0, mode 1 */
    TH0 = 0xEC;  TL0 = 0x78;
    ET0 = 1;  EA = 1;               /* enable Timer 0 interrupt */
    TR0 = 1;                        /* start timer */
    while (1);                      /* everything is done in the ISR */
}

Checked in a simulator: the minutes count increased after 60.0 s. The reload value includes 36 extra counts to compensate for the time between the overflow and the reload in the compiler-generated routine; without it each tick would last about 5036 cycles and the clock would run slow (lose time) by about 0.7 %. A 12 MHz crystal is assumed; a 32.768 kHz RTC chip gives better long-term accuracy.

✓ Answer checked by Claude Opus 5.5 (high effort)

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