BCD-to-7-segment decoder; frequency counter

BCD-to-7-segment decoder

A BCD-to-7-segment decoder is a combinational circuit that converts a 4-bit BCD input (DCBA = 0000 to 1001) into the seven outputs a–g needed to light the segments of a 7-segment display, so that the decimal digit 0–9 appears. Example: input 0101 (5) makes segments a, f, g, c, d active. The 7447 (active-LOW outputs, for common-anode displays) and 7448 (active-HIGH, for common-cathode) are common ICs.

       a
     ─────
  f |     | b       DCBA ─> [7447] ─> a b c d e f g
    |  g  |
     ─────
  e |     | c
    |     |
     ─────
       d

Frequency counter

A frequency counter measures the frequency of a signal by counting how many cycles of the signal occur during an accurately known gate time. If $N$ cycles are counted in gate time $T_g$:

$$f = \frac{N}{T_g}$$

With $T_g = 1$ s, the count $N$ is directly the frequency in Hz.

 Input ─> Amplifier + Schmitt ──────┐
                                    v
 Crystal ─> Time-base ─> Gate ─> ┌─────┐
 osc.       divider     control  │ AND │
                          │  │   └──┬──┘
                          │  │      v
                          │  └─> Decade counters
                          │   reset    │
                          │            v
                          └──────> Latch (strobe)
                                       v
                             BCD-to-7-seg decoders
                                       v
                               7-segment display

Blocks and operation

1. Input shaper – an amplifier and Schmitt trigger convert the unknown input (sine, triangle, etc.) into clean rectangular pulses, one per cycle.
2. Crystal oscillator and time-base divider – a stable oscillator (e.g. 1 MHz) is divided by decade counters to give accurate gate times such as 1 s, 0.1 s or 10 ms.
3. Gate control flip-flop – produces a gate pulse of exactly $T_g$ width.
4. Main AND gate – passes input pulses to the counters only during $T_g$.
5. Decade counters (e.g. 7490) – count the pulses in BCD.
6. Latch – at the end of the gate time a strobe pulse copies the count into the latch so the display stays steady; then a reset pulse clears the counters for the next measurement.
7. BCD-to-7-segment decoders and display – show the latched count, usually as a multiplexed display.

Example: with $T_g = 0.1$ s, if 4,567 pulses are counted, $f = 4567 / 0.1 = 45{,}670$ Hz $= 45.67$ kHz.

A longer gate time gives better resolution ($\pm 1$ count $= \pm 1/T_g$ Hz) but a slower update.