Sequence detector 1101 using SR flip-flops

The machine has one serial input X and one output Z. Z = 1 when the last four bits received are 1, 1, 0, 1. Only SR flip-flops are used.

A Mealy machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so 2 SR flip-flops ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

Step 1: States

Step 2: State diagram

 Main path (label = X/Z):
 A -1/0-> B -1/0-> C -0/0-> D -1/1-> B
 Other transitions:
 A -0/0-> A    B -0/0-> A
 C -1/0-> C    D -0/0-> A

Step 3: State assignment

Step 4: Excitation table

SR excitation: 0→0: S=0, R=X; 0→1: S=1, R=0; 1→0: S=0, R=1; 1→1: S=X, R=0.

Step 5: K-maps (rows $Q_1$, columns $Q_0X$)

Step 6: Equations

$$\begin{aligned} &S_1 = \overline{Q_1}Q_0X,\quad R_1 = Q_1Q_0 \\ &S_0 = Q_1\overline{Q_0}\overline{X} + \overline{Q_1}\overline{Q_0}X,\quad R_0 = \overline{Q_1}Q_0 + Q_0\overline{X} \\ &Z = Q_1Q_0X \end{aligned}$$

Step 7: Logic diagram

   +-----+       +-----+
S0>|S   Q|-Q0 S1>|S   Q|-Q1
   | FF0 |       | FF1 |
R0>|R    |    R1>|R    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
S1 = Q1'.Q0.X   R1 = Q1.Q0
S0 = Q1.Q0'.X' + Q1'.Q0'.X   R0 = Q1'.Q0 + Q0.X'
Z = Q1.Q0.X

The gates for each flip-flop input are built from the equations; the output gate gives Z directly (Mealy output).

Check with an input stream

Z = 1 appears exactly on the clock in which the last bit of 1101 arrives; overlapping sequences are also detected.