Sequence detector 1011 using T flip-flops

The detector watches the serial data stream X and makes Y = 1 when the last four bits received are 1, 0, 1, 1; otherwise Y = 0. Positive-edge triggered T flip-flops are used.

A Mealy machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so 2 T flip-flops ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

Step 1: States

Step 2: State diagram

 Main path (label = X/Y):
 A -1/0-> B -0/0-> C -1/0-> D -1/1-> B
 Other transitions:
 A -0/0-> A    B -1/0-> B
 C -0/0-> A    D -0/0-> C

Step 3: State assignment

Step 4: Excitation table

T excitation: T = 1 when the flip-flop must change, T = 0 when it must hold ($T = Q \oplus Q^+$).

Step 5: K-maps (rows $Q_1$, columns $Q_0X$)

Step 6: Equations

$$\begin{aligned} &T_1 = Q_1Q_0X + Q_1\overline{Q_0}\overline{X} + \overline{Q_1}Q_0\overline{X} \\ &T_0 = Q_0\overline{X} + \overline{Q_0}X \\ &Y = Q_1Q_0X \end{aligned}$$

Step 7: Logic diagram

   +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1
   | FF0 |       | FF1 |
   |     |       |     |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
T1 = Q1.Q0.X + Q1.Q0'.X' + Q1'.Q0.X'
T0 = Q0.X' + Q0'.X
Y = Q1.Q0.X

The gates for each flip-flop input are built from the equations; the output gate gives Y directly (Mealy output).

Check with an input stream

Y = 1 appears exactly on the clock in which the last bit of 1011 arrives; overlapping sequences are also detected.

Note: $T_0 = Q_0 \oplus X$, so FF0 needs only one XOR gate.