Sequence detector 1110 using T flip-flops

A Mealy machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of 1110 arrives. Flip-flops: T.

States (what has been received so far):

• A: reset / last bit 0
• B: "1" received
• C: "11" received
• D: "111" received (stays in D on more 1s)

State diagram (Mealy)

Arc label = input/output

 A --1/0--> B --1/0--> C --1/0--> D --0/1--> A

 A --0/0--> A  (self loop)
 B --0/0--> A
 C --0/0--> A
 D --1/0--> D  (self loop)

State table

State assignment

A = 00, B = 01, C = 10, D = 11 (flip-flop outputs $Q_1 Q_0$).

Excitation table of T flip-flop

Transition and excitation table

K-maps and simplified equations

T1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       1    0
Q1Q0=10       1    0

T0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       1    1
Q1Q0=11       1    0
Q1Q0=10       0    1

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       1    0
Q1Q0=10       0    0

$$\begin{aligned} T_1 &= Q_1 X' + Q_1' Q_0 X \\ T_0 &= Q_0 X' + Q_0' X + Q_1' X \\ Z &= Q_1 Q_0 X' \end{aligned}$$

Logic diagram

           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+

Gates needed (two T flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

• $T_1$: a 2-input AND for $Q_1 X'$; a 3-input AND for $Q_1' Q_0 X$, combined in a 2-input OR gate.
• $T_0$: a 2-input AND for $Q_0 X'$; a 2-input AND for $Q_0' X$; a 2-input AND for $Q_1' X$, combined in a 3-input OR gate.
• $Z$: a 3-input AND for $Q_1 Q_0 X'$.

Check: input X = 0111101110 gives Z = 0000010001; Z = 1 at bits 6 and 10. Note D stays in D on 1, since "1111" still ends in "111".