Sequence detector 1011 using JK flip-flops

A Mealy machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of 1011 arrives. Flip-flops: J-K.

States (what has been received so far):

• A: reset / no useful bits
• B: "1" received
• C: "10" received
• D: "101" received

State diagram (Mealy)

Arc label = input/output

 A --1/0--> B --0/0--> C --1/0--> D --1/1--> B

 A --0/0--> A  (self loop)
 B --1/0--> B  (self loop)
 C --0/0--> A
 D --0/0--> C

State table

State assignment

A = 00, B = 01, C = 10, D = 11 (flip-flop outputs $Q_1 Q_0$).

Excitation table of J-K flip-flop

Transition and excitation table

K-maps and simplified equations

J1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       1    0
Q1Q0=11       x    x
Q1Q0=10       x    x

K1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       x    x
Q1Q0=11       0    1
Q1Q0=10       1    0

J0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       x    x
Q1Q0=11       x    x
Q1Q0=10       0    1

K0          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       1    0
Q1Q0=11       1    0
Q1Q0=10       x    x

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       0    1
Q1Q0=10       0    0

$$\begin{aligned} J_1 &= Q_0 X' \\ K_1 &= Q_0 X + Q_0' X' \\ J_0 &= X \\ K_0 &= X' \\ Z &= Q_1 Q_0 X \end{aligned}$$

Logic diagram

           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+

Gates needed (two J-K flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

• $J_1$: a 2-input AND for $Q_0 X'$.
• $K_1$: a 2-input AND for $Q_0 X$; a 2-input AND for $Q_0' X'$, combined in a 2-input OR gate.
• $J_0$: direct line $X$.
• $K_0$: direct line $X'$.
• $Z$: a 3-input AND for $Q_1 Q_0 X$.

Check: input X = 1011011 gives Z = 0001001; Z = 1 at bits 4 and 7 (overlapping 1011011). From D, input 0 gives "1010" whose useful tail is "10", so D goes to C.