Sequence detector 1011 state diagram and VHDL

A sequence detector reads a serial bit stream x (one bit per clock) and sets output z = 1 when the last four bits are 1011. Overlapping sequences are allowed (1011011 contains two). A Mealy machine with four states is used:

State diagram (Mealy, arc label = input / output)

 main path:
 (S0) -1/0-> (S1) -0/0-> (S10) -1/0-> (S101)
                                         |
               back to (S1) <---- 1/1 ----+

 other arcs:
 S0   --0/0--> S0          S1   --1/0--> S1
 S10  --0/0--> S0          S101 --0/0--> S10

Notes: from S101 the input 1 completes 1011 (z = 1) and the final 1 is the start of a new match, so the next state is S1. From S101 the input 0 gives 1010, whose last two bits "10" are a prefix, so the next state is S10.

State table

VHDL code

library ieee;
use ieee.std_logic_1164.all;

-- Mealy detector for the serial pattern 1011 (overlapping allowed)
entity seq_1011 is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous, active high
    x   : in  std_logic;       -- serial input, one bit per clock
    z   : out std_logic        -- '1' when 1011 has just been received
  );
end entity seq_1011;

architecture fsm of seq_1011 is
  type state_t is (S0, S1, S10, S101);
  signal state, next_state : state_t;
begin
  -- state register
  process (clk, rst)
  begin
    if rst = '1' then
      state <= S0;
    elsif rising_edge(clk) then
      state <= next_state;
    end if;
  end process;

  -- next-state and output logic (Mealy)
  process (state, x)
  begin
    z <= '0';
    case state is
      when S0 =>                       -- nothing matched
        if x = '1' then next_state <= S1; else next_state <= S0; end if;
      when S1 =>                       -- seen 1
        if x = '0' then next_state <= S10; else next_state <= S1; end if;
      when S10 =>                      -- seen 10
        if x = '1' then next_state <= S101; else next_state <= S0; end if;
      when S101 =>                     -- seen 101
        if x = '1' then
          z <= '1';                    -- 1011 detected
          next_state <= S1;            -- last 1 can start a new pattern
        else
          next_state <= S10;           -- 1010: the last "10" is still a prefix
        end if;
    end case;
  end process;
end architecture fsm;

Simulation with GHDL for the input 1011011010110111101101 gave z = 1 at bit positions 4, 7, 12, 15 and 20, each the last bit of a 1011 (positions 4 and 7 overlap: 1011011).