24-hour digital clock

A 24-hour digital clock shows time from 00:00:00 to 23:59:59. It is a chain of counters fed by a 1 Hz time base, with BCD-to-7-segment decoders and displays.

Block diagram

 AC 50 Hz -> [Shaper] -> [÷50] -> 1 Hz
                                  |
   +------------------------------+
   v
 [SECONDS ÷60: ÷10 -> ÷6] --> 1 pulse/min
   |  (2 decoders + 2 displays)
   v
 [MINUTES ÷60: ÷10 -> ÷6] --> 1 pulse/h
   |  (2 decoders + 2 displays)
   v
 [HOURS units ÷10] ---Q3---> [HOURS tens 0-2]
   | U3 U2 U1 U0               | T1 T0
   |       U2 ------+    +---- T1
   |                v    v
   |               [ NAND ]--o CLR (both)
 [7447]+[disp]       [7447]+[disp]

Design of each section

1. 1 Hz time base: the 50 Hz mains is stepped down and squared by a Schmitt trigger, then divided by 50 (÷10 then ÷5) to give 1 pulse per second.
2. Seconds (÷60): mod-10 units counter (0–9) whose $Q_3$ clocks a mod-6 tens counter (0–5, cleared at 0110 by NAND of $Q_2$, $Q_1$). The tens reset gives 1 pulse per minute.
3. Minutes (÷60): identical to the seconds section; gives 1 pulse per hour.
4. Hours (÷24): a mod-10 units counter (U) and a 2-bit tens counter (T: 0, 1, 2). The units $Q_3$ falling at 9 → 0 clocks the tens counter.
   • The count must go 23 → 00. Count 24 = tens 10, units 0100.
   • Between 20 and 24, $T_1 = 1$ and $U_2 = 1$ occur together for the first time at 24. So a NAND gate of $T_1$ and $U_2$ drives the active-low CLEAR of both hour counters:

$$\overline{CLR} = \overline{T_1\,U_2}$$

• Thus the hours count 00, 01, …, 09, 10, …, 19, 20, 21, 22, 23, 00.

5. Display: each BCD output drives a 7447 BCD-to-7-segment decoder and a common-anode display (six digits: HH:MM:SS).