Skip to main content

32:1 MUX from 16:1 and 2:1 MUXes

Short answer

Use two 16:1 MUXes for inputs I0–I15 and I16–I31, both with shared selects S3–S0. A 2:1 MUX with select S4 chooses between their outputs, yielding a 32:1 MUX. No extra gates needed.

Design a 32 to 1 multiplexer using 16 to 1 and 2 to 1 multiplexers.

A 32:1 MUX has inputs I0I_0–I31I_{31} and five select lines S4S3S2S1S0S_4S_3S_2S_1S_0. It is built from two 16:1 MUXes and one 2:1 MUX (a multiplexer tree).

Design

  • Level 1: MUX-1 (16:1) takes I0I_0–I15I_{15}; MUX-2 (16:1) takes I16I_{16}–I31I_{31}. Both share the lower selects S3S2S1S0S_3S_2S_1S_0.
  • Level 2: a 2:1 MUX with select S4S_4 passes MUX-1 output when S4=0S_4 = 0 and MUX-2 output when S4=1S_4 = 1.
             S3 S2 S1 S0
           +-----------+
 I0-I15 -->| 16:1 MUX-1|--P--+      S4
           +-----------+     |   +------+
                             +-->|0     |
           +-----------+         | 2:1  |---> Y
 I16-I31 ->| 16:1 MUX-2|--Q----->|1     |
           +-----------+         +------+
             S3 S2 S1 S0

Output equation

Y=S4′P+S4QY = S_4'P + S_4Q

where P=∑k=015mkIkP = \sum_{k=0}^{15} m_k I_k and Q=∑k=015mkIk+16Q = \sum_{k=0}^{15} m_k I_{k+16}, with mkm_k the minterms of S3S2S1S0S_3S_2S_1S_0.

S4S_4S3S2S1S0S_3S_2S_1S_0Y
00000 – 1111I0I_0 – I15I_{15}
10000 – 1111I16I_{16} – I31I_{31}

Example

S4S3S2S1S0=11001S_4S_3S_2S_1S_0 = 11001 (= 25). MUX-1 gives I9I_9 and MUX-2 gives I25I_{25} (both select input 9). The 2:1 MUX with S4=1S_4 = 1 passes QQ, so Y=I25Y = I_{25}. Correct.

Alternative: if the 16:1 MUXes (e.g. 74150) have enable inputs, connect S4′S_4' to the enable of MUX-1 and S4S_4 to MUX-2, and OR the two outputs instead of using the 2:1 MUX.

✓ Answer checked by Claude Opus 5.5 (high effort)

All Digital Logic chapter 4 questions →