8:1 MUX operation; 32:1 MUX from 8:1

Operation of an 8:1 multiplexer

An 8:1 multiplexer selects one of 8 data inputs $I_0$–$I_7$ and passes it to a single output $Y$. The input is chosen by three select lines $S_2S_1S_0$ ($2^3 = 8$).

$$Y = S_2'S_1'S_0'I_0 + S_2'S_1'S_0I_1 + S_2'S_1S_0'I_2 + S_2'S_1S_0I_3 + S_2S_1'S_0'I_4 + S_2S_1'S_0I_5 + S_2S_1S_0'I_6 + S_2S_1S_0I_7$$

Internally it has eight 4-input AND gates (each gets one data input and one combination of $S_2, S_1, S_0$ or their complements) and one 8-input OR gate. Only the AND gate whose select combination is true is enabled.

 I0..I7 ---->+---------+
             |  8:1    |
             |  MUX    |-----> Y
 S2 S1 S0 -->+---------+   (74151)

32:1 MUX using only 8:1 MUXes

A 32:1 MUX needs 5 select lines $S_4$–$S_0$.

• Level 1: four 8:1 MUXes (M1–M4) take $I_0$–$I_7$, $I_8$–$I_{15}$, $I_{16}$–$I_{23}$, $I_{24}$–$I_{31}$. All use $S_2S_1S_0$.
• Level 2: a fifth 8:1 MUX (M5) selects one of the four outputs. Its select lines are $S_4$, $S_3$ on its two lower selects and its MSB select tied to 0, so only inputs $I_0$–$I_3$ of M5 are used.

                              +-----------+
  I0-I7   -->[M1 8:1]-------->| I0        |
  I8-I15  -->[M2 8:1]-------->| I1        |
  I16-I23 -->[M3 8:1]-------->| I2   M5   |----> Y
  I24-I31 -->[M4 8:1]-------->| I3  (8:1) |
                       0 ---->| I4-I7     |
                              +-----------+
   M1-M4 selects: S2 S1 S0     M5 selects: 0, S4, S3

Total: 5 MUXes of 8:1. Example: $S_4..S_0 = 10110$ gives M3 output $I_{16+6} = I_{22}$, and M5 with $S_4S_3 = 10$ passes M3, so $Y = I_{22}$.