How is a ring counter formed from a shift register?

The last stage output is fed back to the first stage input

The complement of the last stage is fed to the first stage

The first stage output is fed to the last stage

Every stage is clocked by the previous stage output

Why does a ring counter need no decoder, and how many states do n flip-flops give?

Only one output is 1 at a time (self-decoding); n states

Its outputs are in binary code; 2^n states

Only one output is 1 at a time; 2n states

It uses a hidden decoder inside; n^2 states

What happens if a 4-bit ring counter starts at 0000 or 1100?

The pattern circulates forever without becoming the correct sequence

It automatically corrects to 1000

2076 Asoj

Short note: ring counter

Short answer

A ring counter is a shift register with the last output fed back to the first input, circulating a single '1' through the stages. In a 4-bit design starting at 1000, it sequences 1000→0100→0010→0001→1000 (mod‑4). It is self-decoding and requires a preset to a valid state.

Write a short note on ring counter.

A ring counter is a shift register (usually of D flip-flops) whose output of the last stage is fed back to the input of the first stage. It is initialised with a single 1 (e.g. 1000) and this 1 circulates through the flip-flops, one stage per clock.

   +-----------------------------------------+
   |   PRE         CLR       CLR       CLR   |
   |  +-----+   +-----+   +-----+   +-----+  |
   +->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--+
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
 CLK ---^---------^---------^---------^
 Start pulse: PRESET A, CLEAR B, C, D -> 1000

Operation (4-bit): after a preset/clear, QA QB QC QD = 1000. At each clock the bits shift right with $D_A = Q_D$ , giving 1000, 0100, 0010, 0001 and back to 1000.

CLK	QA	QB	QC	QD
0	1	0	0	0
1	0	1	0	0
2	0	0	1	0
3	0	0	0	1
4	1	0	0	0

Features

n flip-flops give n states (mod-n counter), e.g. 4 flip-flops give mod-4.
Only one output is 1 at any time, so it is self-decoding: no decoder gates are needed.
Each output frequency is $f_{CLK}/n$ .
It must be preset to a valid starting pattern; a wrong start (e.g. 0000 or 1100) circulates forever.
Uses: timing/sequence generation, stepper motor control, control-step signals in CPUs.

A variation with $\overline{Q_D}$ fed back (switched tail or Johnson counter) gives 2n states.

✓ Answer checked by Claude Opus 5.5 (high effort)

Shift register uses; switched tail ring counter · Digital Logic, chapter 7
Shift register uses; 4-bit ring counter · Digital Logic, chapter 7

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Short note: ring counter

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