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Temperature effect on carrier concentration

Short answer

In intrinsic semiconductors, carrier concentration rises exponentially with temperature: ni ∝ T^(3/2) exp(-Eg/2kT). In doped semiconductors, three regions emerge: at low T ionisation gives n ∝ exp(-ΔE/2kT); at medium T saturation n ≈ Nd constant; at high T intrinsic generation dominates, n ≈ ni again.

Explain how does temperature affects the formation of carrier concentration in semiconductor.

The carrier concentration in a semiconductor depends strongly on temperature because carriers are created thermally, either by ionising impurities or by breaking covalent bonds across the band gap.

Intrinsic semiconductor

Electron-hole pairs are created when thermal energy lifts electrons across EgE_g:

ni=NcNv exp⁡(−Eg2kT),Nc,Nv∝T3/2n_i = \sqrt{N_cN_v}\,\exp\left(-\frac{E_g}{2kT}\right), \quad N_c, N_v \propto T^{3/2}

so ni∝T3/2e−Eg/2kTn_i \propto T^{3/2}e^{-E_g/2kT}. The exponential dominates: for Si, nin_i roughly doubles for every 8 to 10 K rise near room temperature.

Extrinsic (n-type) semiconductor

A plot of ln⁡n\ln n against 1/T1/T shows three regions:

  1. Low temperature (ionisation or freeze-out region): only some donors are ionised.
n=(12NcNd)1/2exp⁡(−ΔE2kT),ΔE=Ec−Edn = \left(\frac{1}{2}N_cN_d\right)^{1/2}\exp\left(-\frac{\Delta E}{2kT}\right), \quad \Delta E = E_c - E_d
  1. Medium temperature (extrinsic or saturation region): all donors are ionised, n≈Ndn \approx N_d, nearly constant. This range (about 150 K to 500 K for Si with Nd=1015N_d = 10^{15} cm−3^{-3}) is where devices work. It begins at the saturation temperature TsT_s, where the donors become fully ionised.

  2. High temperature (intrinsic region): thermal generation across EgE_g exceeds NdN_d; n≈nin \approx n_i and the material behaves as intrinsic. The changeover temperature TiT_i is where ni≈Ndn_i \approx N_d.

 ln n
   |\
   | \   intrinsic region
   |  \  slope -Eg/2k
   |   \
   |    \____________________  n = Nd
   |       extrinsic region  \
   |                          \   ionisation region
   |                           \  slope -ΔE/2k
   +-----|--------------------|-------- 1/T
        1/Ti                 1/Ts
   (high T at left, low T at right)

Fermi level

As TT rises, EFE_F moves from near EdE_d (low TT) towards mid-gap (high TT), because the extrinsic carriers become a smaller fraction of the total.

The upper limit of device operation is set by TiT_i; wide band gap materials (GaAs, SiC) have higher TiT_i and can work at higher temperatures.

✓ Answer checked by Claude Opus 5.5 (high effort)

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