Short note: DMA controller

Direct Memory Access (DMA) is a technique in which data is transferred directly between an I/O device and memory without the microprocessor handling each byte. A DMA controller (Intel 8257 or 8237) takes control of the system buses for the transfer. It is used for fast, bulk transfers such as disk and display data, where program-controlled or interrupt-driven I/O would be too slow.

Basic operation

1. The device raises DREQ (DMA request) to the controller.
2. The controller sends HOLD to the CPU.
3. The CPU finishes its current machine cycle, floats its buses and replies HLDA (hold acknowledge).
4. The controller sends DACK to the device, places the memory address on the address bus and issues MEMR/MEMW and IOR/IOW signals; data moves directly.
5. The address register is incremented and the count register decremented; when the count reaches zero, the terminal count (TC) signal ends the transfer and the controller releases HOLD. The CPU resumes.

 I/O device <--DREQ/DACK--> DMA controller --HOLD--> CPU
                                  <--HLDA-----------
            data bus <-------> Memory (address by DMAC)

Features of 8257: 4 independent channels, each with a 16-bit address register and 14-bit terminal count register; priority fixed or rotating; modes: read, write, verify.

Transfer types: single-byte (cycle stealing), block (burst) and demand transfer.

Advantages: high speed, CPU is free for other work. Drawback: extra hardware, and the CPU is held off the bus during the transfer.