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Data bus and address bus width

Short answer

Data bus width is the number of bits transferred per cycle, determining data transfer size and performance. Address bus width is the number of address lines, defining the maximum directly addressable memory (2^n locations). For example, 32 address lines yield 4 GB.

What does the width of the data bus / address bus represent in a system?

Data bus width

The data bus width is the number of bits that can be transferred between the CPU and memory or I/O in one bus cycle. It decides the amount of data moved per transfer and so affects performance. A 32-bit data bus moves 4 bytes at a time; a 64-bit bus moves 8 bytes. It usually matches the word size of the processor.

Address bus width

The address bus width is the number of address lines. It decides the maximum number of memory locations the CPU can directly address, which is 2ⁿ for n lines.

  • 16 lines: 2¹⁶ = 64 K locations (8085)
  • 20 lines: 2²⁰ = 1 MB (8086)
  • 32 lines: 2³² = 4 GB

The address bus is unidirectional (CPU to memory), while the data bus is bidirectional.

✓ Answer checked by Claude Opus 5.5 (high effort)

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