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Why simulate resistors with switched capacitors in MOS

Short answer

MOS resistors of MΩ range are too large and inaccurate; switched capacitors give area-efficient, accurate, tunable resistance dependent only on capacitor ratio and clock. A capacitor C switched at frequency fc between two nodes using non-overlapping clocks transfers charge C(V1-V2) each period, yielding average current fc C(V1-V2) and equivalent resistance Req = 1/(fc C).

Why do we need switched capacitor to simulate resistor in MOS technology? How can you simulate a resistor using switched capacitor? Explain with necessary derivations.

Need for switched capacitors in MOS technology

Active-RC filters for audio and voice frequencies need resistors of hundreds of kΩ to MΩ, which MOS ICs cannot provide well:

  • Chip area: diffused or poly resistors have low sheet resistance, so a 1 MΩ resistor occupies a very large area; a switched capacitor giving 10 MΩ needs only about 1 pF.
  • Accuracy: absolute values of on-chip R and C vary by about ±20 %, and the errors are independent, so the RC time constant may be off by ±40 %. With SC, the time constant becomes τ=C/(fcCR)\tau = C/(f_cC_R), which depends only on a capacitor ratio (accurate to about 0.1 % in MOS) and a crystal clock.
  • Temperature and linearity: capacitor ratios track with temperature and voltage; diffused resistors do not.
  • Tunability: changing the clock frequency moves all pole and zero frequencies together.
  • MOS gives near-ideal switches (very high off resistance) and op-amps with high input impedance that hold charge, so SC circuits are natural in MOS.

Simulating a resistor with a switched capacitor (parallel type)

Consider a capacitor CRC_R with two MOS switches driven by non-overlapping clocks ϕ1\phi_1 and ϕ2\phi_2 of frequency fc=1/Tcf_c = 1/T_c:

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND
  1. Phase ϕ1\phi_1 (left switch closed): CRC_R charges to V1V_1; stored charge q1=CRV1q_1 = C_RV_1.
  2. Phase ϕ2\phi_2 (right switch closed): CRC_R charges/discharges to V2V_2; stored charge q2=CRV2q_2 = C_RV_2.
  3. Charge moved from node 1 to node 2 in one clock period:
Δq=q1−q2=CR(V1−V2)\Delta q = q_1 - q_2 = C_R(V_1 - V_2)
  1. If fcf_c is much higher than the signal frequency, V1V_1 and V2V_2 are nearly constant over a period, so the average current is
Iavg=ΔqTc=CRfc(V1−V2)Req=V1−V2Iavg=1fcCR=TcCR\begin{aligned} I_{avg} &= \frac{\Delta q}{T_c} = C_Rf_c(V_1 - V_2) \\ R_{eq} &= \frac{V_1 - V_2}{I_{avg}} = \frac{1}{f_cC_R} = \frac{T_c}{C_R} \end{aligned}

So a capacitor switched at rate fcf_c behaves like a resistor Req=1/(fcCR)R_{eq} = 1/(f_cC_R). Example: CR=1C_R = 1 pF, fc=100f_c = 100 kHz gives Req=10R_{eq} = 10 MΩ.

Other forms: the series switched capacitor gives the same Req=1/(fcCR)R_{eq} = 1/(f_cC_R), and the bilinear type gives Req=1/(4fcCR)R_{eq} = 1/(4f_cC_R).

Conditions: two-phase non-overlapping clock (so the nodes are never shorted together), fc≫f_c \gg highest signal frequency (typically 50–100 times), and the nodes are driven by low-impedance sources such as op-amp outputs or virtual ground.

✓ Answer checked by Claude Sonnet 5.5

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