Why switched capacitors; design for 100–400 rad/s peak

Why resistors are replaced by switched capacitors

• A large resistor (hundreds of kΩ or more) takes a very large chip area, whereas a small capacitor plus two MOS switches takes very little area.
• The absolute values of IC resistors and capacitors vary by ±20 % or more, so an RC time constant is inaccurate. In an SC circuit the time constant is $\tau = C/(C_Rf_c)$, where $C$ is the integrating capacitor. It depends only on a capacitor ratio (accurate to about 0.1 %) and on the clock frequency (crystal-controlled, so very accurate).
• Capacitor ratios track well with temperature and ageing.
• The response can be tuned by changing the clock frequency.
• MOS technology makes good capacitors, switches and op-amps on one chip together with digital circuits.

         phi1        phi2
  V1 o---/ ----+---- / ---o V2
               |
              === C
               |
              GND

Two non-overlapping clock phases $\phi_1$ and $\phi_2$ at frequency $f_c = 1/T$:

• During $\phi_1$ the capacitor connects to $V_1$: charge $q_1 = CV_1$.
• During $\phi_2$ it connects to $V_2$: charge $q_2 = CV_2$.

Charge moved from $V_1$ to $V_2$ in one clock period: $\Delta q = C(V_1 - V_2)$. Average current:

$$I = \frac{\Delta q}{T} = C f_c (V_1 - V_2) \quad\Rightarrow\quad R_{eq} = \frac{V_1 - V_2}{I} = \frac{1}{C f_c} = \frac{T}{C}$$

This holds when $f_c$ is much higher than the signal frequencies.

Transfer function from the Bode plot

Reading the straight-line plot: the slope changes from 0 to +20 dB/dec at ω = 100 (a zero), from +20 to −20 dB/dec at ω = 200 (a double pole), and from −20 back to 0 at ω = 400 (a zero). Check: the rise $20\log(200/100)$ = 6 dB matches the 6 dB peak.

$$T(s) = \frac{(s+100)(s+400)}{(s+200)^2} = \frac{s+100}{s+200}\cdot\frac{s+400}{s+200}$$

DC gain $= 100 \times 400/200^2 = 1$ (0 dB). (The exact peak of this function is about 1.9 dB; the 6 dB is the asymptotic value.)

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: $f_c$ = 10 kHz, $C$ = 100 pF.

Answer: $f_c$ = 10 kHz; section 1: C = 100 pF, $C_{R1}$ = 1 pF, $C_{R2}$ = 2 pF; section 2: C = 100 pF, $C_{R1}$ = 4 pF, $C_{R2}$ = 2 pF (two inverting stages give a positive overall gain).