SC filter applications; design for 100–400 rad/s peak

Applications of switched capacitor filters

SC filters are fully integrated MOS filters whose frequencies are set by capacitor ratios and the clock. Main uses:

• Voice-band filters in telephone systems (PCM codec anti-aliasing and reconstruction filters, DTMF tone decoders).
• Modems, audio equalizers and speech processing ICs.
• Clock-tunable (programmable) filters: changing $f_c$ shifts all frequencies, e.g. MF10, MAX7400 type ICs.
• Mixed-signal ICs: sigma-delta ADCs, sample-and-hold, data acquisition and biomedical front ends.

Design

Reading the Bode plot. Slope +20 dB/decade starts at $\omega = 100$ (a zero). At $\omega = 200$ the slope changes from +20 to −20 dB/decade, a change of −40 dB/decade, so there is a double pole at 200. At $\omega = 400$ the slope returns to 0, so there is a zero at 400. Check: rise from 100 to 200 at 20 dB/decade $= 20\log_{10}2 = 6.02$ dB, which matches the 6 dB peak.

$$\begin{aligned} T(s) &= \frac{(1 + s/100)(1 + s/400)}{(1 + s/200)^2} = \frac{200^2}{100 \times 400}\cdot\frac{(s+100)(s+400)}{(s+200)^2} \\ &= \frac{(s+100)(s+400)}{(s+200)^2} \end{aligned}$$

(gain constant $= 40000/40000 = 1$, so 0 dB at DC and at high frequency.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+100}{s+200}}_{T_1(s)} \times \underbrace{\frac{s+400}{s+200}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break frequency is 400 rad/s ($\approx 64$ Hz). Take $f_c = 10$ kHz (about 157 times higher, so the SC resistor approximation holds). Take $C_1 = C_2 = C = 100$ pF in both stages. Then $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{100\text{ pF}\times 100}{10^4} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 200}{10^4} = 2\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 400}{10^4} = 4\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 200}{10^4} = 2\text{ pF} \end{aligned}$$

(Equivalent resistors: 100 MΩ, 50 MΩ, 25 MΩ, 50 MΩ — far too large to build as diffused resistors, which is why SC is used.)

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 10$ kHz, two-phase non-overlapping ($\phi_1$, $\phi_2$).

Answer: $T(s) = \frac{(s+100)(s+400)}{(s+200)^2}$ realised by two cascaded SC sections with $C_1 = C_2 = 100$ pF, switched capacitors 1 pF & 2 pF (stage 1) and 4 pF & 2 pF (stage 2), $f_c = 10$ kHz. The design follows the asymptotes; the actual peak at $\omega = 200$ is about 1.94 dB because the breaks are only one octave apart.