Switched-Capacitor Filters

Switched-capacitor filter

A switched-capacitor (SC) filter is an active filter in which the resistors of an active-RC filter are replaced by capacitors switched by MOS transistors driven by a clock. Each switched capacitor behaves like a resistor $R = 1/(Cf_c)$, so the time constants depend only on capacitor ratios and the clock frequency.

         phi1        phi2
  V1 o---/ ----+---- / ---o V2
               |
              === C
               |
              GND

Two non-overlapping clock phases $\phi_1$ and $\phi_2$ at frequency $f_c = 1/T$:

• During $\phi_1$ the capacitor connects to $V_1$: charge $q_1 = CV_1$.
• During $\phi_2$ it connects to $V_2$: charge $q_2 = CV_2$.

Charge moved from $V_1$ to $V_2$ in one clock period: $\Delta q = C(V_1 - V_2)$. Average current:

$$I = \frac{\Delta q}{T} = C f_c (V_1 - V_2) \quad\Rightarrow\quad R_{eq} = \frac{V_1 - V_2}{I} = \frac{1}{C f_c} = \frac{T}{C}$$

This holds when $f_c$ is much higher than the signal frequencies.

Design for $T(s) = \dfrac{(s+200)(s+800)}{(s+400)^2}$

Split into two first-order sections:

$$T(s) = \underbrace{\frac{s+200}{s+400}}_{T_1}\cdot\underbrace{\frac{s+800}{s+400}}_{T_2}$$

DC gain $= 200 \times 800/400^2 = 1$ and high-frequency gain $= 1$.

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: clock $f_c$ = 10 kHz (the highest critical frequency, 800 rad/s ≈ 127 Hz, is far below $f_c$), integrating capacitors $C$ = 100 pF.

Each section inverts, so the cascade of two gives $+T(s)$ with the correct sign.

 Vi -->[ T1: C=100p, CR1=2p, CR2=4p ]-->
       [ T2: C=100p, CR1=8p, CR2=4p ]--> Vo
              (fc = 10 kHz)

Answer: $f_c$ = 10 kHz; section 1: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 2 pF, $C_{R2}$ = 4 pF; section 2: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 8 pF, $C_{R2}$ = 4 pF.

Switched-capacitor filter

A switched-capacitor (SC) filter is an active filter in which the resistors of an active-RC filter are replaced by capacitors switched by MOS transistors driven by a clock. Each switched capacitor behaves like a resistor $R = 1/(Cf_c)$, so the time constants depend only on capacitor ratios and the clock frequency.

Applications

• Voice-band filters in telephone PCM codecs and modems.
• Anti-aliasing and reconstruction filtering in data converters; sigma-delta modulators.
• Audio equalisers and tone controls; DTMF (touch-tone) receivers.
• Programmable/tunable filters (cut-off set by the clock) and filter ICs (e.g. MF10 type).
• Biomedical and instrumentation front ends in mixed-signal ICs.

Transfer function from the plot

Slope changes: +20 dB/dec starts at ω = 10 (zero), flat from 100 (pole), −20 dB/dec from 1000 (pole), flat again from 10⁴ (zero). Check: rise $20\log(100/10)$ = 20 dB.

$$T(s) = \frac{(s+10)(s+10^4)}{(s+100)(s+1000)} = \frac{s+10}{s+100}\cdot\frac{s+10^4}{s+1000}$$

DC gain $= 10 \times 10^4/(100 \times 1000) = 1$ and gain at high frequency $= 1$ (0 dB).

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: $f_c$ = 20 kHz (more than 10 times the highest corner, 10⁴ rad/s ≈ 1.6 kHz). Because the corners are spread over three decades, a different $C$ is used in each section to keep the switched capacitors near 1–10 pF.

Answer: $f_c$ = 20 kHz; section 1: $C_1 = C_2$ = 2 nF, $C_{R1}$ = 1 pF, $C_{R2}$ = 10 pF; section 2: $C_1 = C_2$ = 20 pF, $C_{R1}$ = 10 pF, $C_{R2}$ = 1 pF.

Why resistors are replaced by switched capacitors

• A large resistor (hundreds of kΩ) takes a very large chip area; a small capacitor plus two MOS switches takes little area.
• Absolute values of IC resistors and capacitors vary by ±20 % or more, so an RC time constant is inaccurate. In an SC circuit the time constant is $\tau = C_2/(C_Rf_c)$: it depends on a capacitor ratio (accurate to about 0.1 %) and the clock (crystal accurate).
• Good temperature and ageing tracking, since ratios track.
• The response can be tuned by changing the clock frequency.
• MOS technology makes good capacitors, switches and op-amps on one chip with digital circuits.

         phi1        phi2
  V1 o---/ ----+---- / ---o V2
               |
              === C
               |
              GND

Two non-overlapping clock phases $\phi_1$ and $\phi_2$ at frequency $f_c = 1/T$:

• During $\phi_1$ the capacitor connects to $V_1$: charge $q_1 = CV_1$.
• During $\phi_2$ it connects to $V_2$: charge $q_2 = CV_2$.

Charge moved from $V_1$ to $V_2$ in one clock period: $\Delta q = C(V_1 - V_2)$. Average current:

$$I = \frac{\Delta q}{T} = C f_c (V_1 - V_2) \quad\Rightarrow\quad R_{eq} = \frac{V_1 - V_2}{I} = \frac{1}{C f_c} = \frac{T}{C}$$

This holds when $f_c$ is much higher than the signal frequencies.

Transfer function from the Bode plot

Reading the straight-line plot: slope changes from 0 to +20 dB/dec at ω = 100 (a zero), from +20 to −20 dB/dec at ω = 200 (two poles), and from −20 back to 0 at ω = 400 (a zero). Check: rise $20\log(200/100)$ = 6 dB, matching the 6 dB peak.

$$T(s) = \frac{(s+100)(s+400)}{(s+200)^2} = \frac{s+100}{s+200}\cdot\frac{s+400}{s+200}$$

DC gain $= 100 \times 400/200^2 = 1$ (0 dB). (The exact peak of this function is about 1.9 dB; the 6 dB is the asymptotic value.)

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: $f_c$ = 10 kHz, $C$ = 100 pF.

Answer: $f_c$ = 10 kHz; section 1: C = 100 pF, $C_{R1}$ = 1 pF, $C_{R2}$ = 2 pF; section 2: C = 100 pF, $C_{R1}$ = 4 pF, $C_{R2}$ = 2 pF (two inverting stages give a positive overall gain).

Transfer function from the Bode plot

From the straight-line plot: a zero at ω = 400 (slope becomes +20 dB/dec), a double pole at ω = 800 (slope changes to −20 dB/dec), and a zero at ω = 1600 (slope returns to 0). Check: $20\log(800/400)$ = 6 dB peak.

$$T(s) = \frac{(s+400)(s+1600)}{(s+800)^2} = \frac{s+400}{s+800}\cdot\frac{s+1600}{s+800}$$

DC gain $= 400 \times 1600/800^2 = 1$ (0 dB).

Switched-capacitor resistor

In MOS technology each resistor is replaced by a capacitor $C_R$ switched by two non-overlapping clock phases at $f_c$; it transfers charge $C_R(V_1 - V_2)$ each period, so $R_{eq} = 1/(C_Rf_c)$.

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: $f_c$ = 20 kHz (well above 1600 rad/s ≈ 255 Hz), $C$ = 100 pF.

 Vi -->[ T1: C=100p, CR1=2p, CR2=4p ]-->
       [ T2: C=100p, CR1=8p, CR2=4p ]--> Vo
              (fc = 20 kHz)

Answer: $f_c$ = 20 kHz; section 1: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 2 pF, $C_{R2}$ = 4 pF; section 2: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 8 pF, $C_{R2}$ = 4 pF.

Switched-capacitor filter

A switched-capacitor (SC) filter is an active filter in which the resistors of an active-RC filter are replaced by capacitors switched by MOS transistors driven by a clock. Each switched capacitor behaves like a resistor $R = 1/(Cf_c)$, so the time constants depend only on capacitor ratios and the clock frequency. The capacitors, MOS switches and op-amps are all made on one MOS chip.

Applications

• Voice-band filters in PCM telephone codecs, modems and fax.
• Anti-aliasing/reconstruction filters and sigma-delta modulators in data converters.
• Audio equalisers, tone decoders, DTMF receivers.
• Clock-tunable universal filter ICs and programmable filters.
• Filters inside mixed-signal ICs (biomedical, sensor interfaces).

Simulating a resistor with a switched capacitor

         phi1        phi2
  V1 o---/ ----+---- / ---o V2
               |
              === C
               |
              GND

Two non-overlapping clock phases $\phi_1$ and $\phi_2$ at frequency $f_c = 1/T$:

• During $\phi_1$ the capacitor connects to $V_1$: charge $q_1 = CV_1$.
• During $\phi_2$ it connects to $V_2$: charge $q_2 = CV_2$.

Charge moved from $V_1$ to $V_2$ in one clock period: $\Delta q = C(V_1 - V_2)$. Average current:

$$I = \frac{\Delta q}{T} = C f_c (V_1 - V_2) \quad\Rightarrow\quad R_{eq} = \frac{V_1 - V_2}{I} = \frac{1}{C f_c} = \frac{T}{C}$$

This holds when $f_c$ is much higher than the signal frequencies.

Example: $C$ = 1 pF switched at $f_c$ = 100 kHz gives $R_{eq} = 1/(10^{-12} \times 10^5)$ = 10 MΩ, which would need a huge area as a diffused resistor.

Use in an integrator: replacing the input resistor of an RC integrator by $C_1$ gives

$$\frac{V_o}{V_i} = -\frac{1}{sR_{eq}C_2} = -\frac{C_1 f_c}{C_2}\cdot\frac{1}{s}$$

so the time constant $C_2/(C_1f_c)$ depends only on a capacitor ratio and the clock, which is very accurate.

Switched-capacitor filter

A switched-capacitor (SC) filter is an active filter in which the resistors of an active-RC filter are replaced by capacitors switched by MOS transistors driven by a clock. Each switched capacitor behaves like a resistor $R = 1/(Cf_c)$, so the time constants depend only on capacitor ratios and the clock frequency.

The basic SC resistor (charge $C_1(V_1 - V_2)$ moved each clock period) gives $R_{eq} = 1/(C_1f_c)$. The building blocks below use the parasitic-insensitive four-switch branch: capacitor $C_1$ with two switches on each plate.

        S1        C1        S3
 Vi o---/ ---+---| |---+---/ ---o to (-) of op-amp
             |         |        (virtual ground)
             / S2      / S4
             |         |
            GND       GND

Inverting integrator

Switching: $\phi_1$: S2 and S4 closed (C1 discharged). $\phi_2$: S1 and S3 closed: $C_1$ charges to $V_i$ through the virtual ground, so charge $C_1V_i$ is pushed onto the feedback capacitor $C_2$ with negative sign.

$$H(z) = -\frac{C_1}{C_2}\cdot\frac{1}{1 - z^{-1}} \qquad\approx\qquad H(s) = -\frac{C_1 f_c}{C_2}\cdot\frac{1}{s}$$

Non-inverting integrator

Change the phases of the left switches: $\phi_1$: S1 and S4 closed ($C_1$ charges to $V_i$ with its right plate grounded). $\phi_2$: S2 and S3 closed (left plate grounded, right plate to the virtual ground). The charge is now delivered with the opposite polarity, one half-period later:

$$H(z) = +\frac{C_1}{C_2}\cdot\frac{z^{-1}}{1 - z^{-1}} \qquad\approx\qquad H(s) = +\frac{C_1 f_c}{C_2}\cdot\frac{1}{s}$$

                    +-----| C2 |-----+
                    |                |
 Vi o--[SC branch C1]--+---(-)       |
                       |      A -----+--o Vo
                 GND--(+)

Summer (and summing integrator)

Connect several SC branches $C_1, C_2, \dots$ (one per input) to the same virtual-ground node. The charges add:

• With a feedback capacitor $C_F$ only: summing integrator $V_o = -\dfrac{f_c}{s}\left(\dfrac{C_1}{C_F}V_1 + \dfrac{C_2}{C_F}V_2\right)$.
• With $C_F$ reset each period (a switch across $C_F$), or with an SC resistor in feedback: summer (amplifier) $V_o = -\left(\dfrac{C_1}{C_F}V_1 + \dfrac{C_2}{C_F}V_2\right)$.

A branch wired with non-inverting phasing gives a + sign for that input, so sums and differences are both possible with one op-amp. All gains are capacitor ratios, hence accurate.

Applications of switched capacitor filters

SC filters are fully integrated MOS filters whose frequencies are set by capacitor ratios and the clock. Main uses:

• Voice-band filters in telephone systems (PCM codec anti-aliasing and reconstruction filters, DTMF tone decoders).
• Modems, audio equalizers and speech processing ICs.
• Clock-tunable (programmable) filters: changing $f_c$ shifts all frequencies, e.g. MF10, MAX7400 type ICs.
• Mixed-signal ICs: sigma-delta ADCs, sample-and-hold, data acquisition and biomedical front ends.

Design

Reading the Bode plot. Slope +20 dB/decade starts at $\omega = 100$ (a zero). At $\omega = 200$ the slope changes from +20 to −20 dB/decade, a change of −40 dB/decade, so there is a double pole at 200. At $\omega = 400$ the slope returns to 0, so there is a zero at 400. Check: rise from 100 to 200 at 20 dB/decade $= 20\log_{10}2 = 6.02$ dB, which matches the 6 dB peak.

$$\begin{aligned} T(s) &= \frac{(1 + s/100)(1 + s/400)}{(1 + s/200)^2} = \frac{200^2}{100 \times 400}\cdot\frac{(s+100)(s+400)}{(s+200)^2} \\ &= \frac{(s+100)(s+400)}{(s+200)^2} \end{aligned}$$

(gain constant $= 40000/40000 = 1$, so 0 dB at DC and at high frequency.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+100}{s+200}}_{T_1(s)} \times \underbrace{\frac{s+400}{s+200}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break frequency is 400 rad/s ($\approx 64$ Hz). Take $f_c = 10$ kHz (about 157 times higher, so the SC resistor approximation holds). Take $C_1 = C_2 = C = 100$ pF in both stages. Then $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{100\text{ pF}\times 100}{10^4} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 200}{10^4} = 2\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 400}{10^4} = 4\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 200}{10^4} = 2\text{ pF} \end{aligned}$$

(Equivalent resistors: 100 MΩ, 50 MΩ, 25 MΩ, 50 MΩ — far too large to build as diffused resistors, which is why SC is used.)

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 10$ kHz, two-phase non-overlapping ($\phi_1$, $\phi_2$).

Answer: $T(s) = \frac{(s+100)(s+400)}{(s+200)^2}$ realised by two cascaded SC sections with $C_1 = C_2 = 100$ pF, switched capacitors 1 pF & 2 pF (stage 1) and 4 pF & 2 pF (stage 2), $f_c = 10$ kHz. The design follows the asymptotes; the actual peak at $\omega = 200$ is about 1.94 dB because the breaks are only one octave apart.

Reading the Bode plot. The response is 0 dB up to $\omega = 10$, then falls at −20 dB/decade (a pole at 10), becomes flat at $\omega = 100$ (a zero at 100), stays at −20 dB to $\omega = 1000$, then rises at +20 dB/decade (a zero at 1000) and flattens at $\omega = 10^4$ (a pole at $10^4$). Check: 10 → 100 is one decade, giving −20 dB.

$$\begin{aligned} T(s) &= \frac{(1 + s/100)(1 + s/1000)}{(1 + s/10)(1 + s/10^4)} = \frac{10 \times 10^4}{100 \times 1000}\cdot\frac{(s+100)(s+1000)}{(s+10)(s+10^4)} \\ &= \frac{(s+100)(s+1000)}{(s+10)(s+10^4)} \end{aligned}$$

(gain constant $= 10^5/10^5 = 1$, so 0 dB at DC and at high frequency.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+100}{s+10}}_{T_1(s)} \times \underbrace{\frac{s+1000}{s+10^4}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is $10^4$ rad/s ($\approx 1.6$ kHz); take $f_c = 100$ kHz. Because the breaks span three decades, choose $C = 10$ nF in stage 1 and $C = 100$ pF in stage 2 so that no switched capacitor is below 1 pF. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{10\text{ nF}\times 100}{10^5} = 10\text{ pF}, & C_{R2} &= \frac{10\text{ nF}\times 10}{10^5} = 1\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 1000}{10^5} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 10^4}{10^5} = 10\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 100$ kHz, two-phase non-overlapping. Equivalent resistors: stage 1 — 1 MΩ and 10 MΩ; stage 2 — 10 MΩ and 1 MΩ.

Answer: $T(s) = \frac{(s+100)(s+1000)}{(s+10)(s+10^4)}$, realised as two cascaded SC first-order sections (values in the table) at $f_c = 100$ kHz. Only capacitor ratios ($C_R/C$) set the break frequencies, so the response is accurate on a MOS chip. Check of the actual curve: $|T|$ at $\omega = 316$ rad/s is −19.18 dB, close to the −20 dB asymptote.

Reading the Bode plot. 0 dB up to $\omega = 10^2$, then +20 dB/decade (a zero at $10^2$) up to 20 dB at $10^3$ where it flattens (a pole at $10^3$). It stays at 20 dB to $10^4$, then falls at −20 dB/decade (a pole at $10^4$) back to 0 dB at $10^5$ (a zero at $10^5$).

$$\begin{aligned} T(s) &= \frac{(1 + s/10^2)(1 + s/10^5)}{(1 + s/10^3)(1 + s/10^4)} = \frac{10^3 \times 10^4}{10^2 \times 10^5}\cdot\frac{(s+10^2)(s+10^5)}{(s+10^3)(s+10^4)} \\ &= \frac{(s+100)(s+10^5)}{(s+1000)(s+10^4)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 1000/100 = 10 = 20$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+100}{s+1000}}_{T_1(s)} \times \underbrace{\frac{s+10^5}{s+10^4}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is $10^5$ rad/s ($\approx 15.9$ kHz); take $f_c = 1$ MHz. Take $C = 10$ nF in stage 1 and $C = 100$ pF in stage 2. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{10\text{ nF}\times 100}{10^6} = 1\text{ pF}, & C_{R2} &= \frac{10\text{ nF}\times 1000}{10^6} = 10\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 10^5}{10^6} = 10\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 10^4}{10^6} = 1\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 1$ MHz, two-phase non-overlapping. Equivalent resistors: stage 1 — 1 MΩ and 100 kΩ; stage 2 — 100 kΩ and 1 MΩ.

Answer: $T(s) = \frac{(s+100)(s+10^5)}{(s+1000)(s+10^4)}$, realised by two cascaded SC sections with the capacitors above and $f_c = 1$ MHz. Actual gain at the band centre ($\omega \approx 3162$ rad/s) is 19.18 dB, close to the 20 dB asymptote.

Switched capacitor filter

A switched capacitor (SC) filter is an active filter in which every resistor of an active-RC filter is replaced by a capacitor and MOS switches driven by a two-phase non-overlapping clock. The switched capacitor behaves like a resistor $R = 1/(f_cC)$, so the filter needs only op-amps, capacitors and switches, all easily built on one MOS chip.

Design

Reading the plot. $\pm 6$ dB/octave $= \pm 20$ dB/decade. The response reaches 20 dB at $\omega = 10$ after rising at 20 dB/decade from 0 dB, so the rise starts one decade earlier: a zero at $\omega = 1$ and a pole at $\omega = 10$. It stays flat to $10^4$ (a pole at $10^4$) and falls at 20 dB/decade, reaching 0 dB one decade later (a zero at $10^5$). (Assumption: the response is 0 dB at very low and very high frequencies, as drawn.)

$$\begin{aligned} T(s) &= \frac{(1 + s/1)(1 + s/10^5)}{(1 + s/10)(1 + s/10^4)} = \frac{10 \times 10^4}{1 \times 10^5}\cdot\frac{(s+1)(s+10^5)}{(s+10)(s+10^4)} \\ &= \frac{(s+1)(s+10^5)}{(s+10)(s+10^4)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 10 = 20$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+1}{s+10}}_{T_1(s)} \times \underbrace{\frac{s+10^5}{s+10^4}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is $10^5$ rad/s ($\approx 15.9$ kHz); take $f_c = 1$ MHz. Stage 1 has very low breaks (1 and 10 rad/s), so it needs a large $C$: take $C = 1\ \mu$F in stage 1 and $C = 100$ pF in stage 2. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{1\ \mu\text{F}\times 1}{10^6} = 1\text{ pF}, & C_{R2} &= \frac{1\ \mu\text{F}\times 10}{10^6} = 10\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 10^5}{10^6} = 10\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 10^4}{10^6} = 1\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 1$ MHz. Equivalent resistors: stage 1 — 1 MΩ and 100 kΩ; stage 2 — 100 kΩ and 1 MΩ. Note: the 1 µF capacitor (spread $10^6$) is too large for a chip; in practice stage 1 is run from a slower clock (e.g. $f_c = 10$ kHz gives $C = 10$ nF with the same $C_R$ values) after an anti-aliasing stage.

Answer: $T(s) = \frac{(s+1)(s+10^5)}{(s+10)(s+10^4)}$, two cascaded SC first-order sections with the values in the table. Actual gain at $\omega \approx 316$ rad/s is 19.99 dB.

Switched capacitor filter

A switched capacitor (SC) filter is an active filter in which every resistor of an active-RC filter is replaced by a capacitor and MOS switches driven by a two-phase non-overlapping clock. The switched capacitor behaves like a resistor $R = 1/(f_cC)$, so the filter needs only op-amps, capacitors and switches, all easily built on one MOS chip.

Applications

• Voice-band filters in telephone systems (PCM codec anti-aliasing and reconstruction filters, DTMF tone decoders).
• Modems, audio equalizers and speech processing ICs.
• Clock-tunable (programmable) filters: changing $f_c$ shifts all frequencies, e.g. MF10, MAX7400 type ICs.
• Mixed-signal ICs: sigma-delta ADCs, sample-and-hold, data acquisition and biomedical front ends.

Design

Reading the plot. The rise from 0 dB at 1000 to 6 dB at 2000 is 6 dB per octave = 20 dB/decade, so there is a zero at 1000 and a pole at 2000. The flat part ends at 4000 (a pole) and the response falls back to 0 dB at 8000 (a zero).

$$\begin{aligned} T(s) &= \frac{(1 + s/1000)(1 + s/8000)}{(1 + s/2000)(1 + s/4000)} = \frac{2000 \times 4000}{1000 \times 8000}\cdot\frac{(s+1000)(s+8000)}{(s+2000)(s+4000)} \\ &= \frac{(s+1000)(s+8000)}{(s+2000)(s+4000)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 2 = 6.02$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+1000}{s+2000}}_{T_1(s)} \times \underbrace{\frac{s+8000}{s+4000}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is 8000 rad/s ($\approx 1.27$ kHz); take $f_c = 100$ kHz. Take $C_1 = C_2 = C = 100$ pF in both stages. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{100\text{ pF}\times 1000}{10^5} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 2000}{10^5} = 2\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 8000}{10^5} = 8\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 4000}{10^5} = 4\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 100$ kHz, two-phase non-overlapping. Equivalent resistors: 10 MΩ, 5 MΩ (stage 1) and 1.25 MΩ, 2.5 MΩ (stage 2).

Answer: $T(s) = \frac{(s+1000)(s+8000)}{(s+2000)(s+4000)}$, two cascaded SC sections, $C = 100$ pF, switched capacitors 1, 2, 8, 4 pF, $f_c = 100$ kHz. Because the breaks are only one octave apart, the real curve is smoother than the asymptotes (3.52 dB at $\omega \approx 2828$ rad/s).