SC MOS filter for 400–1600 rad/s peak

Transfer function from the Bode plot

From the straight-line plot: a zero at ω = 400 (slope becomes +20 dB/dec), a double pole at ω = 800 (slope changes to −20 dB/dec), and a zero at ω = 1600 (slope returns to 0). Check: $20\log(800/400)$ = 6 dB peak.

$$T(s) = \frac{(s+400)(s+1600)}{(s+800)^2} = \frac{s+400}{s+800}\cdot\frac{s+1600}{s+800}$$

DC gain $= 400 \times 1600/800^2 = 1$ (0 dB).

Switched-capacitor resistor

In MOS technology each resistor is replaced by a capacitor $C_R$ switched by two non-overlapping clock phases at $f_c$; it transfers charge $C_R(V_1 - V_2)$ each period, so $R_{eq} = 1/(C_Rf_c)$.

Building block

A first-order section with an op-amp, input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$:

$$T(s) = -\frac{Y_1}{Y_2} = -\frac{C_1}{C_2}\cdot\frac{s + 1/(R_1C_1)}{s + 1/(R_2C_2)}$$

With $C_1 = C_2 = C$ the zero is at $a = 1/(R_1C)$ and the pole at $b = 1/(R_2C)$. Each resistor is then replaced by a switched capacitor $C_R = 1/(Rf_c)$, i.e.

$$C_{R1} = \frac{aC}{f_c}, \qquad C_{R2} = \frac{bC}{f_c}$$

            +-------| C2 |-------+
            +----[SC: CR2]-------+
            |                    |
 Vi o--+--| C1 |--+              |
       |          |              |
       +-[SC: CR1]+-----(-)      |
                          A -----+----o Vo
                 GND-----(+)

Choices: $f_c$ = 20 kHz (well above 1600 rad/s ≈ 255 Hz), $C$ = 100 pF.

 Vi -->[ T1: C=100p, CR1=2p, CR2=4p ]-->
       [ T2: C=100p, CR1=8p, CR2=4p ]--> Vo
              (fc = 20 kHz)

Answer: $f_c$ = 20 kHz; section 1: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 2 pF, $C_{R2}$ = 4 pF; section 2: $C_1 = C_2$ = 100 pF, $C_{R1}$ = 8 pF, $C_{R2}$ = 4 pF.