SC filter: 6 dB between 2000 and 4000 rad/s

Switched capacitor filter

A switched capacitor (SC) filter is an active filter in which every resistor of an active-RC filter is replaced by a capacitor and MOS switches driven by a two-phase non-overlapping clock. The switched capacitor behaves like a resistor $R = 1/(f_cC)$, so the filter needs only op-amps, capacitors and switches, all easily built on one MOS chip.

Applications

• Voice-band filters in telephone systems (PCM codec anti-aliasing and reconstruction filters, DTMF tone decoders).
• Modems, audio equalizers and speech processing ICs.
• Clock-tunable (programmable) filters: changing $f_c$ shifts all frequencies, e.g. MF10, MAX7400 type ICs.
• Mixed-signal ICs: sigma-delta ADCs, sample-and-hold, data acquisition and biomedical front ends.

Design

Reading the plot. The rise from 0 dB at 1000 to 6 dB at 2000 is 6 dB per octave = 20 dB/decade, so there is a zero at 1000 and a pole at 2000. The flat part ends at 4000 (a pole) and the response falls back to 0 dB at 8000 (a zero).

$$\begin{aligned} T(s) &= \frac{(1 + s/1000)(1 + s/8000)}{(1 + s/2000)(1 + s/4000)} = \frac{2000 \times 4000}{1000 \times 8000}\cdot\frac{(s+1000)(s+8000)}{(s+2000)(s+4000)} \\ &= \frac{(s+1000)(s+8000)}{(s+2000)(s+4000)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 2 = 6.02$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+1000}{s+2000}}_{T_1(s)} \times \underbrace{\frac{s+8000}{s+4000}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is 8000 rad/s ($\approx 1.27$ kHz); take $f_c = 100$ kHz. Take $C_1 = C_2 = C = 100$ pF in both stages. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{100\text{ pF}\times 1000}{10^5} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 2000}{10^5} = 2\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 8000}{10^5} = 8\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 4000}{10^5} = 4\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 100$ kHz, two-phase non-overlapping. Equivalent resistors: 10 MΩ, 5 MΩ (stage 1) and 1.25 MΩ, 2.5 MΩ (stage 2).

Answer: $T(s) = \frac{(s+1000)(s+8000)}{(s+2000)(s+4000)}$, two cascaded SC sections, $C = 100$ pF, switched capacitors 1, 2, 8, 4 pF, $f_c = 100$ kHz. Because the breaks are only one octave apart, the real curve is smoother than the asymptotes (3.52 dB at $\omega \approx 2828$ rad/s).