SC filter: 6 dB between 1000 and 2000 rad/s

Importance of switched capacitor filters

• Large resistors (MΩ) are impossible to make in small chip area; an SC "resistor" of 10 MΩ needs only about 1 pF.
• Pole and zero frequencies depend on capacitor ratios and the clock ($\omega = f_cC_R/C$), which MOS technology makes accurate to about 0.1 %, unlike absolute R and C (±20 %).
• The whole filter (op-amps, capacitors, switches) fits on one MOS chip with digital circuits, at low cost and low power.
• The response is tunable by the clock frequency, making programmable filters easy (telephone codecs, modems, audio).

Design

Reading the plot. The rise from 0 dB at 500 to 6 dB at 1000 is 6 dB/octave = 20 dB/decade: a zero at 500 and a pole at 1000. The flat part ends at 2000 (a pole) and the response falls back to 0 dB at 4000 (a zero).

$$\begin{aligned} T(s) &= \frac{(1 + s/500)(1 + s/4000)}{(1 + s/1000)(1 + s/2000)} = \frac{1000 \times 2000}{500 \times 4000}\cdot\frac{(s+500)(s+4000)}{(s+1000)(s+2000)} \\ &= \frac{(s+500)(s+4000)}{(s+1000)(s+2000)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 2 = 6.02$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+500}{s+1000}}_{T_1(s)} \times \underbrace{\frac{s+4000}{s+2000}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is 4000 rad/s ($\approx 637$ Hz); take $f_c = 50$ kHz. Take $C_1 = C_2 = C = 100$ pF in both stages. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{100\text{ pF}\times 500}{5\times 10^4} = 1\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 1000}{5\times 10^4} = 2\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 4000}{5\times 10^4} = 8\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 2000}{5\times 10^4} = 4\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 50$ kHz, two-phase non-overlapping. Equivalent resistors: 20 MΩ, 10 MΩ (stage 1) and 2.5 MΩ, 5 MΩ (stage 2).

Answer: $T(s) = \frac{(s+500)(s+4000)}{(s+1000)(s+2000)}$, two cascaded SC sections with $C = 100$ pF, switched capacitors 1, 2, 8, 4 pF and $f_c = 50$ kHz. (Actual gain at $\omega \approx 1414$ rad/s is 3.52 dB, as the breaks are only an octave apart.)