SC MOS filter: 20 dB between 10³ and 10⁴ rad/s

Reading the Bode plot. 0 dB up to $\omega = 10^2$, then +20 dB/decade (a zero at $10^2$) up to 20 dB at $10^3$ where it flattens (a pole at $10^3$). It stays at 20 dB to $10^4$, then falls at −20 dB/decade (a pole at $10^4$) back to 0 dB at $10^5$ (a zero at $10^5$).

$$\begin{aligned} T(s) &= \frac{(1 + s/10^2)(1 + s/10^5)}{(1 + s/10^3)(1 + s/10^4)} = \frac{10^3 \times 10^4}{10^2 \times 10^5}\cdot\frac{(s+10^2)(s+10^5)}{(s+10^3)(s+10^4)} \\ &= \frac{(s+100)(s+10^5)}{(s+1000)(s+10^4)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 1000/100 = 10 = 20$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+100}{s+1000}}_{T_1(s)} \times \underbrace{\frac{s+10^5}{s+10^4}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is $10^5$ rad/s ($\approx 15.9$ kHz); take $f_c = 1$ MHz. Take $C = 10$ nF in stage 1 and $C = 100$ pF in stage 2. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{10\text{ nF}\times 100}{10^6} = 1\text{ pF}, & C_{R2} &= \frac{10\text{ nF}\times 1000}{10^6} = 10\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 10^5}{10^6} = 10\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 10^4}{10^6} = 1\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 1$ MHz, two-phase non-overlapping. Equivalent resistors: stage 1 — 1 MΩ and 100 kΩ; stage 2 — 100 kΩ and 1 MΩ.

Answer: $T(s) = \frac{(s+100)(s+10^5)}{(s+1000)(s+10^4)}$, realised by two cascaded SC sections with the capacitors above and $f_c = 1$ MHz. Actual gain at the band centre ($\omega \approx 3162$ rad/s) is 19.18 dB, close to the 20 dB asymptote.