SC filter with ±6 dB/octave slopes and 20 dB band

Switched capacitor filter

A switched capacitor (SC) filter is an active filter in which every resistor of an active-RC filter is replaced by a capacitor and MOS switches driven by a two-phase non-overlapping clock. The switched capacitor behaves like a resistor $R = 1/(f_cC)$, so the filter needs only op-amps, capacitors and switches, all easily built on one MOS chip.

Design

Reading the plot. $\pm 6$ dB/octave $= \pm 20$ dB/decade. The response reaches 20 dB at $\omega = 10$ after rising at 20 dB/decade from 0 dB, so the rise starts one decade earlier: a zero at $\omega = 1$ and a pole at $\omega = 10$. It stays flat to $10^4$ (a pole at $10^4$) and falls at 20 dB/decade, reaching 0 dB one decade later (a zero at $10^5$). (Assumption: the response is 0 dB at very low and very high frequencies, as drawn.)

$$\begin{aligned} T(s) &= \frac{(1 + s/1)(1 + s/10^5)}{(1 + s/10)(1 + s/10^4)} = \frac{10 \times 10^4}{1 \times 10^5}\cdot\frac{(s+1)(s+10^5)}{(s+10)(s+10^4)} \\ &= \frac{(s+1)(s+10^5)}{(s+10)(s+10^4)} \end{aligned}$$

(gain constant $= 1$; mid-band gain $= 10 = 20$ dB.)

Building block (first-order SC section). An inverting op-amp stage with input admittance $Y_1 = sC_1 + 1/R_1$ and feedback admittance $Y_2 = sC_2 + 1/R_2$ gives

$$\begin{aligned} T(s) &= -\frac{Y_1}{Y_2} = -\frac{sC_1 + 1/R_1}{sC_2 + 1/R_2} = -\frac{C_1}{C_2}\cdot\frac{s + \frac{1}{R_1C_1}}{s + \frac{1}{R_2C_2}} \end{aligned}$$

Each resistor is replaced by a switched capacitor clocked at $f_c$ (two-phase, non-overlapping clock), for which $R = \frac{1}{f_c C_R}$. Then

$$T(s) = -\frac{sC_1 + f_cC_{R1}}{sC_2 + f_cC_{R2}}, \qquad \omega_z = \frac{f_cC_{R1}}{C_1}, \quad \omega_p = \frac{f_cC_{R2}}{C_2}$$

With $C_1 = C_2 = C$ the high-frequency gain is 1 and $C_{R1} = \frac{C\,\omega_z}{f_c}$, $C_{R2} = \frac{C\,\omega_p}{f_c}$. Two inverting stages in cascade give a positive overall gain.

Splitting into two first-order sections:

$$T(s) = \underbrace{\frac{s+1}{s+10}}_{T_1(s)} \times \underbrace{\frac{s+10^5}{s+10^4}}_{T_2(s)}$$

Choice of clock and capacitors. Highest break is $10^5$ rad/s ($\approx 15.9$ kHz); take $f_c = 1$ MHz. Stage 1 has very low breaks (1 and 10 rad/s), so it needs a large $C$: take $C = 1\ \mu$F in stage 1 and $C = 100$ pF in stage 2. With $C_R = C\omega/f_c$:

$$\begin{aligned} \text{Stage 1: } C_{R1} &= \frac{1\ \mu\text{F}\times 1}{10^6} = 1\text{ pF}, & C_{R2} &= \frac{1\ \mu\text{F}\times 10}{10^6} = 10\text{ pF} \\ \text{Stage 2: } C_{R1} &= \frac{100\text{ pF}\times 10^5}{10^6} = 10\text{ pF}, & C_{R2} &= \frac{100\text{ pF}\times 10^4}{10^6} = 1\text{ pF} \end{aligned}$$

Final circuit (two identical-form stages in cascade; each SC resistor is the toggle-switch circuit shown):

                    C2
            +-------||------+
            |               |
            +---[CR2-SC]----+
            |               |
       C1   |   |\          |
 Vi -+--||--+---|-\         |
     |      |   |  >--------+---> Vo
     +[CR1]-+ +-|+/
      (SC)    | |/
             GND

       phi1          phi2
 V1 ----o/o----+----o/o---- V2
               |
              ===  CR
               |
              GND

Clock: $f_c = 1$ MHz. Equivalent resistors: stage 1 — 1 MΩ and 100 kΩ; stage 2 — 100 kΩ and 1 MΩ. Note: the 1 µF capacitor (spread $10^6$) is too large for a chip; in practice stage 1 is run from a slower clock (e.g. $f_c = 10$ kHz gives $C = 10$ nF with the same $C_R$ values) after an anti-aliasing stage.

Answer: $T(s) = \frac{(s+1)(s+10^5)}{(s+10)(s+10^4)}$, two cascaded SC first-order sections with the values in the table. Actual gain at $\omega \approx 316$ rad/s is 19.99 dB.