- 2075 Baisakh · 16 marks
Lead compensator for satellite position control
Short answer
D(z) = 8.294(z-0.8)/(z+0.1816). The compensator places dominant closed-loop poles at 0.7077±j0.2189, yielding damping ratio ζ=0.707, natural frequency ωn=4.24 rad/s, and time constant 0.33 s.
A control system block diagram shown in figure below is of satellite communication system. Design a lead compensator D(z) to stabilize a satellite position. The sampling rate of digital controller is 10 samples per second. Consider design criteria: (i) damping ratio must be greater than 0.6, (ii) damped natural frequency should not exceed 1 Hz i.e. ωd<0.1ωₙ, and the time constant for the closed loop control system should be less than 0.5 second with 5% criterion for settling time. [Figure: summing junction → D(z) → ZOH → 0.02/s (volts to rps) → 1/s (rps to rev) → output; feedback through gain 360 (degrees) to the negative input; sampler T = 0.1 s; sketch of a satellite dish]
The satellite is a double integrator. With proportional control alone the loop is only marginally stable, so a lead compensator () is designed by the z-plane root-locus method.
Plant and loop gain
The loop is ZOH, then , then , then the feedback gain 360. The loop transfer function is
For a ZOH followed by :
The two poles at give two branches that leave the unit circle, so the uncompensated system cannot be stabilised by gain alone.
Translating the specifications
- : choose .
- Time constant s (5% settling time s): choose , so the time constant is 0.333 s and s.
- rad/s (1 Hz): with , rad/s (0.48 Hz). This is satisfied.
So rad/s and
Angle deficiency
| Factor | Angle at |
|---|---|
| zero at | |
| double pole at | |
| Plant total |
The compensator must add of phase lead.
Placing the zero and pole
Put the zero at (near , which reduces the pull of the double pole):
- angle of is
- the pole must give :
Gain
Check
- Characteristic equation has roots (designed) and (fast, negligible).
- Simulated step response (T = 0.1 s): settles within 5% in about 1.1 s, which meets s. The peak is about 1.36 at s. This overshoot is larger than alone predicts because of the closed-loop zeros at 0.8 and −1, which are usual for a type-2 loop.
- The acceleration constant is , so steady-state error is zero for step and ramp commands.
r -->(+)-->[D(z)]-->[ZOH]-->[0.02/s]-->[1/s]--+--> c
^- |
+-----------------[360]<-----------------+
Answer: , giving dominant poles (, rad/s, time constant 0.33 s).
✓ Answer checked by Claude Opus 5.5 (high effort)
Related questions
- Controller design with 8 samples per cycle, step response and Kv · Digital Control System, chapter 4
- Root-locus design: 8 samples per cycle, T = 0.2 s · Digital Control System, chapter 4
- Digital control system block diagram and advantages · Digital Control System, chapter 1 · asked 3×
- Digital PI design, plant e^(−5s)/(s+0.4), step response · Digital Control System, chapter 4
- Digital PD controller design for plant 1/s² · Digital Control System, chapter 4 · asked 2×
- Digital PI design, plant e^(−5s)/(s+0.4), Kv · Digital Control System, chapter 4 · asked 2×
- Block diagram of digital communication system · Data Communication, chapter 1 · asked 8×
- Lead compensator for K/[s(1+0.2s)], Kv=10, PM=50° · Control Systems, chapter 7 · asked 2×
- Reasons for modulation; digital communication block diagram · Communication Systems, chapter 1
- Digital vs analog communication; DCS block diagram · Communication Systems, chapter 1