Chapter 4 · 10 hours
Design and Compensation of Discrete Time Control System
IOE past exam questions
Past questions and answers
38 questions set from this chapter, 7 of them more than once. Most asked first.
- Asked 6 times
- 2082 Chaitra (new course) · 5 marks
- 2082 Chaitra · 5 marks
- 2082 Kartik · 5 marks
- 2078 Chaitra · 8 marks
- 2074 Bhadra · 8 marks
- 2071 Magh · 8 marks
Consider the digital filter defined by G(z)=(2+2.2z⁻¹+0.2z⁻²)/(1+0.4z⁻¹-0.12z⁻²) (equivalently GD(z)=(2z²+2.2z+0.2)/(z²+0.4z-0.12)). Realize this filter in the ladder scheme.
Answer
In ladder programming, is written as a continued fraction in :
Each becomes a delay , and each becomes a constant gain.
Write the filter in positive powers of :
Step 1: Constant term
So .
Step 2:
So . The remainder is (exactly ).
Step 3:
So .
Step 4: and
So and .
| 2 | 0.7143 | 16.333 | 0.0357 | −20 |
Ladder block diagram
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - |
| |
+<--E2--[1/A2]<-------------+
Signal equations (these define the ladder diagram; marks a take-off point):
With the values: , , , .
Simulating these equations gives the same impulse response as the original difference equation . The realization needs only 2 delays.
- Asked 3 times
- 2082 Chaitra · 12 marks
- 2076 Bhadra · 12 marks
- 2073 Bhadra · 12 marks
Design a digital controller such that the compensated system should have damping ratio ζ=0.5 and settling time tₛ=2 s using root locus approach. [Figure: unity-feedback loop: R(s) → summing junction → E(s) → sampler (T = 0.2) → digital controller → ZOH → 1/s(s+2) → C(s)]
Answer
Step 1: Desired closed-loop poles
From the specifications and s (2% criterion, ):
With s, the samples per cycle are .
Step 2: Plant pulse transfer function
Step 3: Angle deficiency at
| Factor | Angle at |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The angle condition requires , so the controller must add of phase lead.
Step 4: Lead controller
Take . Put the zero on the plant pole, , to cancel it. This zero adds . The pole must then contribute :
Step 5: Gain from the magnitude condition
After cancellation, the open-loop function is , and at :
Step 6: Check
The roots are , the desired poles. ✔ This is a second-order closed loop, so the poles are exactly dominant.
Static velocity error constant:
Answer: , a lead compensator, with .
- Asked 3 times
- 2081 Chaitra · 12 marks
- 2074 Bhadra · 12 marks
- 2082 Kartik · 12 marks
Design a digital PI controller such that the dominant closed loop poles have damping ratio ζ=0.5, sampling period T = 1 and ωd/ωₛ=1/10 (10 samples per cycle of sinusoidal oscillation) and dead time of 2 sec. Also find Kᵥ and eₛₛ in response to unit ramp input. [Figure: unity-feedback loop: sampler → GD(z) → ZOH (1-e⁻ᵀˢ)/s → e⁻²ˢ/(s+1) → output]
Answer
Step 1: Plant pulse transfer function ( s)
The dead time of 2 s is exactly , so it becomes :
Step 2: Desired dominant poles
With 10 samples per cycle, , and
Step 3: PI controller and angle condition
Angles at :
| Factor | Angle |
|---|---|
| double pole at origin () | |
| pole at | |
| controller pole at | |
| Sum of pole angles |
For , the controller zero must contribute :
Step 4: Gain
Step 5: and steady-state error for a ramp
Check: the closed-loop characteristic equation has roots , and . The desired pair is obtained. The real pole at 0.7562 is close to the PI zero at 0.5873 and partly cancelled by it, but it makes the response a little slower than the pair alone suggests.
Answer: (that is, , ), with and for a unit ramp.
- Asked 2 times
- 2082 Chaitra · 3 marks
- 2077 Chaitra · 4 marks
Realize the given digital controller by series programming: G(z)=4(z-1)(z²+1.2z+1)/((z+0.1)(z²-0.3z+0.8)).
Answer
In series (cascade) programming, is factored into first- and second-order sections. Each section is realized by standard programming, and the sections are connected in cascade.
Step 1: Factor into sections (divide each factor by the highest power of )
Step 2: Difference equations
Section 1: with
Section 2: input , intermediate
Step 3: Block diagram (two standard-programmed sections in cascade)
Section 1, :
x(k)-->(S)------------o--[1]-------->(S)--> y1(k)
^ | ^
| [z^-1] |
| | w1(k-1) |
+<[-0.1]------o--[-1]---------+
Section 2, , followed by the gain 4:
y1(k)-->(S)------------o--[1]-------->(S)->[4]-> y(k)
^ | ^
| [z^-1] |
| | w2(k-1) |
(S)<[0.3]------o--[1.2]------>(S)
^ | ^
| [z^-1] |
| | w2(k-2) |
+<[-0.8]------o--[1]----------+
The realization uses only delay elements, the minimum for a third-order filter. The overall gain 4 can be placed at either end.
Why series programming
- A coefficient error in one section moves only that section's poles and zeros. The structure is less sensitive to coefficient quantization than direct programming of the whole third-order polynomial.
- The complex poles (with ) are kept together in one real-coefficient second-order section.
- Asked 2 times
- 2081 Chaitra · 5 marks
- 2078 Chaitra · 4 marks
Consider the digital filter defined by parallel programming: Y(z)/X(z)=4(z-1)(z²+1.2z+1)/((z+0.1)(z²-0.3z+0.8)).
Answer
In parallel programming, is expanded into partial fractions in . Each term is realized separately (first- or second-order), and the outputs are added.
Step 1: Write in powers of
The numerator and denominator have equal degree. So there is a constant term, plus a first-order term for the real pole and a second-order term for the complex pair, .
Step 2: Partial fractions (let )
- and : at , , so . At (that is, , where ): , so .
Check: At , both forms give the same value. At : . ✔
Step 3: Difference equations of the branches
- , and
- , and
Step 4: Block diagram
Overall structure:
+-------------[-50]-------------+ y1
| v
x(k)-o--+-->[ 46.619/(1+0.1z^-1) ]--->(S)--> y(k)
| y2 ^
+-->[ second-order branch ]-----+ y3
Branch 2:
x(k)-->(S)------------o--[1]-------->(S)->[46.619]-> y2(k)
^ |
| [z^-1]
| | w2(k-1)
+<[-0.1]------o
Branch 3:
x(k)-->(S)------------o--[7.381]---->(S)--> y3(k)
^ | ^
| [z^-1] |
| | w3(k-1) |
(S)<[0.3]------o--[4.0476]-----+
^ |
| [z^-1]
| | w3(k-2)
+<[-0.8]------o
Total delays: , the minimum for a third-order controller. A coefficient error in one branch affects only that branch's pole(s).
- Asked 2 times
- 2071 Magh · 10 marks
- 2070 Magh · 12 marks
Design a digital controller such that the compensated system should have damping ratio ζ=0.5 and settling time = 2 seconds of the following system using root locus approach. [Figure: unity-feedback loop: R(s) → summing junction → E(s) → sampler (period T) → digital controller G₁*(s) → ZOH → 1/s(s+1) → C(s)]
Answer
The sampling period is not given, so we choose it first.
Step 1: Desired poles and choice of
From and s:
Choose s. Then rad/s, giving about 9 samples per damped cycle. This is fast enough (the usual rule is at least 8–10), and the ZOH adds little phase lag.
Step 2: Plant with ZOH
Step 3: Angle condition at
| Factor | Angle |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The angle deficiency is , so a lead controller is needed.
Step 4: Lead controller
Cancel the slow plant pole with the zero: , which adds . The controller pole must give :
Step 5: Gain
Step 6: Check
The open loop is . The characteristic equation is , whose roots are . ✔
Answer (for s): . The closed-loop poles are at (, s), and . A different changes the numbers but not the method.
- Asked 2 times
- 2080 Chaitra · 12 marks
- 2075 Bhadra · 12 marks
Design a digital proportional-plus-derivative controller for the plant as shown in figure below. It is desired that the damping ratio ζ of the dominant closed loop poles be 0.5 and the undamped natural frequency be 4 rad/sec. The sampling period is 0.1 sec. [Figure: R(z) → summing junction → sampler (T) → digital PD controller → ZOH (1-e⁻ᵀˢ)/s → 1/s² → C(z); feedback path H(s) (unity in the 2080 paper)]
Answer
Step 1: Plant with ZOH ( s)
Step 2: Desired closed-loop poles
With and :
Step 3: Digital PD controller
Step 4: Angle condition at
| Factor | Angle |
|---|---|
| plant zero at | |
| double plant pole at | |
| controller pole at | |
| Sum |
For a total of , the controller zero must give :
The zero lies almost directly below the desired pole.
Step 5: Magnitude condition
Step 6: PD gains
Step 7: Check
The roots are (the desired pair) and . The third pole is much closer to the origin, so it decays fast, and the complex pair is dominant. ✔
Answer: , i.e. and . The difference equation is .
- 2080 Chaitra · 8 marks
Realize the given digital filter by ladder programming: G(z)=(2+2.2z⁻¹+0.2z⁻²)/(1+0.4z⁻¹-0.1z⁻²).
Answer
In positive powers of :
Ladder programming expands as:
Step 1:
Step 2:
The remainder is (exactly ). So .
Step 3:
So .
Step 4: and
So and .
| 2 | 0.7143 | 12.25 | 0.07033 | −16.25 |
Ladder block diagram
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - |
| |
+<--E2--[1/A2]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
Numerical gains: , , , .
Substituting back reproduces exactly, so the realization is correct. It uses two delay elements.
- 2076 Bhadra · 2+6 marks
Higher order pulse transfer functions are generally realized by decomposing it in to several lower order pulse transfer function why? Consider a digital filter shown below. Realize this filter in ladder scheme. G(z)=(2+2.2z⁻¹+0.2z⁻²)/(1+0.4z⁻¹-0.12z⁻²)
Answer
Why higher-order pulse transfer functions are decomposed
A high-order realized directly (direct or standard programming) is very sensitive to coefficient errors. The controller coefficients are stored with finite word length. A small rounding error in one coefficient of a high-order denominator can move all the poles a lot, even outside the unit circle, and make the filter unstable. So the transfer function is split into first- and second-order blocks (series, parallel or ladder programming):
- A coefficient error then affects only the one or two poles of that block.
- The structure is less sensitive to quantization, and the computations are better conditioned.
- Low-order blocks are easier to program, test and scale.
Ladder realization
Write the filter in positive powers of :
In ladder programming, is expanded as a continued fraction:
Each is realized by a delay , and each by a constant.
Step 1: .
So .
Step 2: .
So .
Step 3: .
So .
Step 4: and .
So and .
| 2 | 0.7143 | 16.333 | 0.0357 | −20 |
Ladder diagram:
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - |
| |
+<--E2--[1/A2]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
With the values: , , , . Only two delays are needed.
The ladder needs only two delays. Because of its continued-fraction structure, it has low sensitivity to coefficient rounding.
- 2073 Magh · 6 marks
Consider the digital filter defined by G(z)=(2+2.2z⁻¹+0.2z⁻²)/(1+0.4z⁻¹-0.12z⁻²). Realize this filter in the parallel scheme.
Answer
In parallel programming, is expanded into partial fractions in , and each term is realized as a separate branch.
Step 1: Factor the denominator
The poles are and .
Step 2: Partial fractions
The numerator and denominator have the same degree in , so
Let .
Check at : . ✔
Step 3: Difference equations
Step 4: Block diagram
Overall structure (three branches added):
+-------------[-1.6667]-------------+
| v
x(k)-o--+-->[ 4.5/(1-0.2z^-1) ]----------->(S)--> y(k)
| ^
+-->[ -0.8333/(1+0.6z^-1) ]---------+
Branch 1:
x(k)-->(S)------------o--[1]-------->(S)->[4.5]-> y1(k)
^ |
| [z^-1]
| | w1(k-1)
+<[0.2]-------o
Branch 2:
x(k)-->(S)------------o--[1]-------->(S)->[-0.8333]-> y2(k)
^ |
| [z^-1]
| | w2(k-1)
+<[-0.6]------o
Two delays are used, one per pole.
- 2072 Asoj · 8 marks
Consider the digital filter defined by G(z)=(2+2.2z⁻¹+0.2z⁻²)/(1+0.4z⁻¹-0.12z⁻²). Realize this filter in the parallel scheme and ladder scheme.
Answer
Given:
(a) Parallel scheme
In parallel programming, is expanded into partial fractions in , and each term is realized as a separate branch.
Step 1: Factor the denominator
The poles are and .
Step 2: Partial fractions The numerator and denominator have the same degree in , so
Let .
Check at : . ✔
Step 3: Difference equations
Step 4: Block diagram Overall structure (three branches added):
+-------------[-1.6667]-------------+
| v
x(k)-o--+-->[ 4.5/(1-0.2z^-1) ]----------->(S)--> y(k)
| ^
+-->[ -0.8333/(1+0.6z^-1) ]---------+
Branch 1:
x(k)-->(S)------------o--[1]-------->(S)->[4.5]-> y1(k)
^ |
| [z^-1]
| | w1(k-1)
+<[0.2]-------o
Branch 2:
x(k)-->(S)------------o--[1]-------->(S)->[-0.8333]-> y2(k)
^ |
| [z^-1]
| | w2(k-1)
+<[-0.6]------o
Two delays are used, one per pole.
(b) Ladder scheme
Write the filter in positive powers of :
In ladder programming, is expanded as a continued fraction:
Each is realized by a delay , and each by a constant.
Step 1: .
So .
Step 2: .
So .
Step 3: .
So .
Step 4: and .
So and .
| 2 | 0.7143 | 16.333 | 0.0357 | −20 |
Ladder diagram:
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - |
| |
+<--E2--[1/A2]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
With the values: , , , . Only two delays are needed.
- 2081 Chaitra · 3 marks
Realize the given digital controller by direct programming: Y(z)/X(z)=(6z²+7z)/(10z³-6z²+7z+5).
Answer
Direct programming realizes the difference equation exactly as written. It uses one chain of delays for past inputs and another for past outputs.
Step 1: Write in powers of
Divide the numerator and denominator by :
Step 2: Difference equation
Step 3: Block diagram (direct programming)
x(k)
o (S)--------------o--> y(k)
| ^ |
[z^-1] | [z^-1]
| x(k-1) | | y(k-1)
o--[0.6]------>(S)<[0.6]--------o
| ^ |
[z^-1] | [z^-1]
| x(k-2) | | y(k-2)
o--[0.7]------>(S)<[-0.7]-------o
^ |
| [z^-1]
| | y(k-3)
+<[-0.5]--------o
- The left delay chain stores and . The right chain stores , and .
- Feed-forward gains are 0.6 and 0.7. Feedback gains are , and (the negatives of the denominator coefficients).
- There is no direct path from to , because the term of the numerator is zero.
- Direct programming needs delays. Standard programming would need only 3.
- 2079 Chaitra · 8 marks
Consider the digital filter defined by G(z)=(6z²+7z)/(10z³+6z²+7z+5). Realize this filter in the standard and series scheme.
Answer
Divide by :
(a) Standard programming
Introduce an intermediate variable :
x(k)-->(S)------------o
^ |
| [z^-1]
| | w(k-1)
(S)<[-0.6]-----o--[0.6]------>(S)--> y(k)
^ | ^
| [z^-1] |
| | w(k-2) |
(S)<[-0.7]-----o--[0.7]--------+
^ |
| [z^-1]
| | w(k-3)
+<[-0.5]------o
Only delays are used, the minimum number.
(b) Series programming
Factor the denominator. Its real root, found numerically, is :
The quadratic has complex roots , so it is kept as one second-order block. The numerator is . So
Check: , and . ✔
Difference equations:
- , and
Block (with gain 0.6):
x(k)-->(S)------------o--[1]-------->(S)->[0.6]-> y1(k)
^ |
| [z^-1]
| | w1(k-1)
+<[-0.6697]---o
Block :
y1(k)-->(S)------------o
^ |
| [z^-1]
| | w2(k-1)
(S)<[0.0697]---o--[1]-------->(S)--> y(k)
^ | ^
| [z^-1] |
| | w2(k-2) |
+<[-0.7467]---o--[1.1667]-----+
The series form also uses 3 delays. Each block is first- or second-order, so it is less sensitive to coefficient rounding.
- 2076 Bhadra · 4 marks
Realize the given digital controller by direct programming: Y(z)/X(z)=(6z²+7z+16)/(10z³+8z²+9z+15).
Answer
Step 1: Write in powers of
Divide the numerator and denominator by :
Step 2: Difference equation
Step 3: Block diagram (direct programming)
x(k)
o (S)--------------o--> y(k)
| ^ |
[z^-1] | [z^-1]
| x(k-1) | | y(k-1)
o--[0.6]------>(S)<[-0.8]-------o
| ^ |
[z^-1] | [z^-1]
| x(k-2) | | y(k-2)
o--[0.7]------>(S)<[-0.9]-------o
| ^ |
[z^-1] | [z^-1]
| x(k-3) | | y(k-3)
o--[1.6]------>(S)<[-1.5]-------o
- The input delay chain gives , , , with gains 0.6, 0.7, 1.6.
- The output delay chain gives , , , fed back with gains , , .
- All products are added in the summer column to give . There is no direct term.
Direct programming uses delays. (The denominator has roots and , which are outside the unit circle, so this filter is unstable as given. The question asks only for its realization.)
- 2075 Baisakh · 8 marks
Realize the digital filter by ladder programming: G(z)=(128z⁻³+224z⁻²+106z⁻¹+11)/(128z⁻³+160z⁻²+34z⁻¹+1).
Answer
Assumption: the textbook form of this filter has positive powers of :
This gives a stable filter (poles , , ) and integer ladder constants. If the form is used literally, the same continued-fraction steps apply but the constants are not integers.
For a third-order filter, ladder programming expands as:
Step 1:
So .
Step 2:
So .
Step 3:
So .
Step 4:
So .
Step 5:
So .
Step 6: and
So and .
| 1 | 2 | 4 | 1 | 2 | 2 | 4 |
Ladder block diagram
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - | +
| v
o<--E2--[1/A2]<----------- (S4)
| ^ -
v + |
(S5)-->[z^-1/B3]-------------o Y3
^ - |
| |
+<--E3--[1/A3]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
With the values: , , , , , . Three delays are used.
Simulating these equations gives the same impulse response as .
- 2075 Bhadra · 6 marks
Assume that a digital filter is given by the following difference equation: y(k)+a₁y(k-1)+a₂y(k-2)=b₁x(k)+b₂x(k)+b₂x(k-1). Draw block diagrams for the filters using (i) standard programming and (ii) ladder programming.
Answer
The difference equation as printed has a typo. It is read as the standard second-order filter
(i) Standard programming
Let :
x(k)-->(S)------------o--[b0]------->(S)--> y(k)
^ | ^
| [z^-1] |
| | w(k-1) |
(S)<[-a1]------o--[b1]------->(S)
^ | ^
| [z^-1] |
| | w(k-2) |
+<[-a2]-------o--[b2]---------+
Only 2 delays are used, the minimum for second order.
(ii) Ladder programming
Expand as a continued fraction:
Define , , and . Then:
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - |
| |
+<--E2--[1/A2]<-------------+
Example: For , , , , : , , , . This gives , , , , .
- 2073 Bhadra · 8 marks
Realize the given digital controller by ladder programming whose transfer function is (8z³+7z²+10z+6)/(4z³+6z²+9z+10).
Answer
Ladder programming expands as a continued fraction:
with .
Step 1:
Step 2:
So .
Step 3:
So .
Step 4:
So .
Step 5:
So .
Step 6: and
So and .
| 2 | −0.8 | 12.5 | −0.02051 | −3.8604 | 0.05031 | −10.04 |
Ladder block diagram
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - | +
| v
o<--E2--[1/A2]<----------- (S4)
| ^ -
v + |
(S5)-->[z^-1/B3]-------------o Y3
^ - |
| |
+<--E3--[1/A3]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
Numerical gains: , , , , , .
The expansion was checked by substituting back. It reproduces exactly, and the ladder's impulse response matches the direct difference equation. Three delays are used.
- 2071 Bhadra · 5 marks
Construct the block diagram for the following pulse-transfer function system (a digital filter) by direct programming: G(z)=(2-0.6z⁻¹)/(1+0.5z⁻¹).
Answer
Step 1: Difference equation
Step 2: Direct programming block diagram
Each delayed input and output term is formed with its own delay element and added in a summer:
x(k)
o--[2]-------->(S)--------------o--> y(k)
| ^ |
[z^-1] | [z^-1]
| x(k-1) | | y(k-1)
o--[-0.6]----->(S)<[-0.5]-------o
- Feed-forward: with gain 2, and with gain .
- Feedback: with gain .
- Direct programming uses delays.
For comparison, standard programming needs only one delay: and .
The pole at is inside the unit circle, so the filter is stable.
- 2068 Magh · 8 marks
Realize system having pulse transfer function G(z)=(z+3)(z²-2z+10)/((z-5)(z²-z+8)) by series programming.
Answer
In series programming, the pulse transfer function is split into a cascade of first- and second-order sections. Each section is realized by standard programming.
Step 1: Split into sections (in powers of )
The quadratics have complex roots, so they stay as one second-order section with real coefficients.
Step 2: Difference equations
Section 1 (input , output ):
Section 2 (input , output ):
Step 3: Block diagram
Section 1:
x(k)-->(S)------------o--[1]-------->(S)--> y1(k)
^ | ^
| [z^-1] |
| | w1(k-1) |
+<[5]---------o--[3]----------+
Section 2:
y1(k)-->(S)------------o--[1]-------->(S)--> y(k)
^ | ^
| [z^-1] |
| | w2(k-1) |
(S)<[1]--------o--[-2]------->(S)
^ | ^
| [z^-1] |
| | w2(k-2) |
+<[-8]--------o--[10]---------+
x(k) --> [ G1(z) ] --y1(k)--> [ G2(z) ] --> y(k)
A total of 3 delays are used. The order of the sections can be swapped.
Note: The poles are and (with ), all outside the unit circle. So this system is unstable, although it can still be realized.
- 2068 Jestha · 8 marks
Realize the following transfer function by series programming: X(z)=(z+1)(z²+3z+7)/((z-2)(z²+z+9)).
Answer
In series programming, (the given pulse transfer function) is split into cascaded low-order sections. Each section is realized by standard programming.
Step 1: Sections in powers of
Both quadratics have complex roots, so each is kept as one second-order factor.
Step 2: Difference equations
Let be the input and the output.
Section 1:
Section 2:
Step 3: Block diagram
Section 1:
u(k)-->(S)------------o--[1]-------->(S)--> y1(k)
^ | ^
| [z^-1] |
| | w1(k-1) |
+<[2]---------o--[1]----------+
Section 2:
y1(k)-->(S)------------o--[1]-------->(S)--> y(k)
^ | ^
| [z^-1] |
| | w2(k-1) |
(S)<[-1]-------o--[3]-------->(S)
^ | ^
| [z^-1] |
| | w2(k-2) |
+<[-9]--------o--[7]----------+
u(k) --> [ G1(z) ] --y1(k)--> [ G2(z) ] --> y(k)
Three delay elements are used. Each section can be scaled and checked separately.
Note: The poles and lie outside the unit circle, so the system is unstable. The series structure is still a valid realization.
- 2067 Mangsir · 10 marks
Realize the following transfer function by ladder programming: X(z)=(z³+4z²+10z+7)/(z³+3z²+11z+18).
Answer
Ladder programming expands as a continued fraction:
Step 1:
Step 2:
So .
Step 3:
So .
Step 4:
So .
Step 5:
So .
Step 6: and
So and .
| 1 | 1 | 0.25 | −0.6154 | −0.5216 | −2.0392 | −0.3395 |
Exact values: , , , .
Ladder block diagram
X(z)--o-----------------[A0]--------------->(S)--> Y(z)
| ^
v + | Y1
(S1)-->[z^-1/B1]-------------o----------+
^ - | +
| v
o<--E1--[1/A1]<----------- (S2)
| ^ -
v + |
(S3)-->[z^-1/B2]-------------o Y2
^ - | +
| v
o<--E2--[1/A2]<----------- (S4)
| ^ -
v + |
(S5)-->[z^-1/B3]-------------o Y3
^ - |
| |
+<--E3--[1/A3]<-------------+
Signal equations of the ladder ( = take-off point, (S) = summer):
Gains in the diagram: , , , , , .
Substituting back reproduces exactly. Three delays are used.
- 2079 Chaitra · 12 marks
Consider the digital control system shown in figure below. In the z plane, design a digital controller such that the dominant closed-loop poles have a damping ratio of 0.5 and a settling time of 2 seconds. The sampling period is assumed to be 0.2 sec. Also, obtain the static velocity error constant of the system. [Figure: unity-feedback loop: r(t) → summing junction → e(t) → sampler → e(kT) → digital controller → ZOH → 1/s(s+2) → C(t)]
Answer
Step 1: Desired closed-loop poles
With and s:
With s:
Step 2: ZOH + plant
Step 3: Angle deficiency
At : the zero gives , the pole at 1 gives , and the pole at 0.6703 gives . The total is . The controller must supply (lead).
Step 4: Lead controller
Choose to cancel the plant pole. This contributes . The controller pole must then contribute :
Step 5: Gain
Step 6: Check
The characteristic equation gives . ✔
Step 7: Static velocity error constant
Answer: and . The steady-state error for a unit ramp is .
- 2082 Chaitra (new course) · 9 marks
Consider a digital control system shown in figure below. The plant is a second order system described as G(s)=1/s(s+1). The sampling period of the system is taken to be T = 1 s. Design a digital controller such that the dominant closed loop poles of the system will have damping ratio ζ=0.5 and number of samples per cycle of damped sinusoidal oscillation to be 8. Following the design, obtain the unit step response of the designed system and static velocity error constant Kᵥ. [Figure: unity-feedback loop: R(s) → summing junction → sampler (T = 1 s) → digital controller → ZOH → G(s) → Y(s)]
Answer
Step 1: Plant pulse transfer function ( s)
Step 2: Desired poles
With 8 samples per cycle, , and
Step 3: Angle condition
| Factor | Angle at |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The controller must add , so a lead compensator is needed.
Step 4: Lead controller
The zero cancels the plant pole at 0.3679 and adds . The controller pole must contribute :
Step 5: Gain
Step 6: Closed-loop pulse transfer function
The poles are , as desired. ✔
Step 7: Unit step response
With , the difference equation is , where :
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0.294 | 0.769 | 1.078 | 1.163 | 1.115 | 1.038 | 0.987 | 0.973 | 0.981 | 0.994 |
The maximum overshoot is about 16.3% at , which matches . One damped cycle takes about 8 samples, and (type-1 system).
Step 8: Static velocity error constant
Answer: . The step response overshoots by 16.3% and settles to 1, and .
- 2073 Magh · 12 marks
Using the root locus method in z-plane determine a digital controller for a system shown below so that the dominant closed loop poles of the compensated system will have damping ratio of 0.5 and number of samples per cycle of damped sinusoidal oscillation to be 8. Assume that the sampling period T as 0.2 sec. [Figure: unity-feedback loop: R(z) → summing junction → sampler → digital controller → zero order hold → 1/s(s+1) → C(z)]
Answer
Step 1: Desired dominant poles
With 8 samples per cycle, , and
With s, this means rad/s, rad/s, and s.
Step 2: Plant with ZOH ( s)
Step 3: Angle deficiency at
| Factor | Angle |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The deficiency is , so a lead compensator is needed.
Step 4: Controller
The zero cancels the pole at 0.8187 and adds . The controller pole must then contribute :
Step 5: Gain
Step 6: Check
The characteristic equation is , with roots . ✔
Answer: , a lead compensator, with .
- 2078 Chaitra · 12 marks
Design a suitable digital controller that includes an integral control action. The design specifications are that the damping ratio of the closed loop poles be 0.5 and there will be at least eight samples per cycle of the damped sinusoidal oscillations. The sampling time is assumed to be 0.2 sec. [Figure: unity-feedback loop: R(z) → summing junction → sampler (T) → digital controller → (1-e⁻ᵀˢ)/s → 10/((s+1)(s+5)) → C(z)]
Answer
Step 1: Plant with ZOH ( s)
Step 2: Desired poles
With and 8 samples per cycle:
Step 3: Try PI alone
Integral action requires a controller pole at . With a PI controller cancelling the slow plant pole, the angle at is:
This is not . There is too much lag, so PI alone cannot place the poles. A lead part is added, which makes the controller PID-like.
Step 4: Controller with integral + lead action
Both plant poles are cancelled. The angle condition at is:
Step 5: Gain
Step 6: Check
The characteristic equation is , with roots . ✔ That is with exactly 8 samples per cycle.
The pole at gives zero steady-state error for a step input.
Answer: , with .
- 2077 Chaitra · 12 marks
Consider a digital control system shown below. By choosing a reasonable sampling period T, design a digital PI controller such that the dominant closed loop poles have a damping ratio ζ of 0.5 and the number of samples per cycle of damped sinusoidal oscillation is 10. Also find the static velocity error constant. [Figure: unity-feedback loop: R(z) → summing junction → sampler (T) → digital PI controller → (1-e⁻ᵀˢ)/s → e⁻⁵ˢ/(s+0.4) → C(z)]
Answer
Step 1: Choice of sampling period
The plant has time constant s and dead time 5 s. Choose s:
- The dead time is then exactly , giving a clean .
- , which gives simple numbers.
- With 10 samples per cycle, the oscillation period is 25 s. This is reasonable for a process with 5 s dead time.
A smaller such as 1 s is not suitable. The dead time becomes , the phase lag at the desired point exceeds what a single PI zero can make up, and the angle condition cannot be met.
Step 2: Desired poles (ζ = 0.5, 10 samples per cycle)
Step 3: PI controller
Angles at :
- double pole at origin:
- pole at 0.3679:
- pole at 1:
The sum is , so the PI zero must add :
Step 4: Gain
so and .
Step 5: Static velocity error constant
The steady-state error for a unit ramp is .
Check: the closed-loop roots are (as designed), and . The real pole near the PI zero (0.5873) is only partly cancelled and adds a slow tail.
Answer (with s): and .
- 2072 Asoj · 12 marks
Consider the digital control system as shown in figure below, where the plant is of the first order and has a dead time of 5 second. By choosing reasonable sampling time T, design a digital PI controller such that the dominant closed loop poles have a damping ratio ζ of 0.5 and the number of samples per cycle of damped oscillation is 10. After the controller is designed, determine the response of the system to a unit step input. [Figure: unity-feedback loop: r(t)/R(z) → summing junction → sampler (δT = T) → digital PI controller → ZOH → e⁻⁵ˢ/(s+0.4) → c(t)/C(z)]
Answer
A digital PI controller is designed by the root-locus (angle and magnitude) method in the z-plane. The plant is (time constant 2.5 s, dead time 5 s).
Choice of sampling period
- The dead time should be a whole number of sampling periods, so .
- Ten samples per cycle fixes the angle of the desired pole at , whatever T is. Each sample of delay () then adds of phase lag at that pole.
- With s () the delay alone gives . The poles at and add more than again, and one PI zero cannot make up the difference, so no PI controller exists.
- Choose s: this equals the plant time constant, the dead time is , and the angle condition can be met.
Pulse transfer function of the plant (with ZOH)
With :
Desired closed-loop poles
(This gives rad/s and rad/s.)
Angle condition
Open loop: . Pole angles at :
| Pole | Angle at |
|---|---|
| (double) | |
| Total |
The zero must give :
Magnitude condition
So and .
Unit-step response
Closed-loop poles: (designed), and . Solving the difference equation with :
| k | 0–2 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 12 | 15 | 20 | 29 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| c(kT) | 0 | 0.320 | 0.571 | 0.795 | 0.907 | 0.958 | 0.962 | 0.947 | 0.957 | 0.987 | 0.997 | 1.000 |
- Output is zero for 3 samples (2 for the dead time, 1 for ZOH plus computation).
- The extra real pole at 0.7562 slows the final approach, so the response rises to about 0.96, dips slightly and creeps up to 1 with almost no overshoot.
- Because of the integral action, steady-state error to a step is zero: . .
Answer: s, (, ); the step response settles at 1 with zero steady-state error.
- 2075 Baisakh · 16 marks
A control system block diagram shown in figure below is of satellite communication system. Design a lead compensator D(z) to stabilize a satellite position. The sampling rate of digital controller is 10 samples per second. Consider design criteria: (i) damping ratio must be greater than 0.6, (ii) damped natural frequency should not exceed 1 Hz i.e. ωd<0.1ωₙ, and the time constant for the closed loop control system should be less than 0.5 second with 5% criterion for settling time. [Figure: summing junction → D(z) → ZOH → 0.02/s (volts to rps) → 1/s (rps to rev) → output; feedback through gain 360 (degrees) to the negative input; sampler T = 0.1 s; sketch of a satellite dish]
Answer
The satellite is a double integrator. With proportional control alone the loop is only marginally stable, so a lead compensator () is designed by the z-plane root-locus method.
Plant and loop gain
The loop is ZOH, then , then , then the feedback gain 360. The loop transfer function is
For a ZOH followed by :
The two poles at give two branches that leave the unit circle, so the uncompensated system cannot be stabilised by gain alone.
Translating the specifications
- : choose .
- Time constant s (5% settling time s): choose , so the time constant is 0.333 s and s.
- rad/s (1 Hz): with , rad/s (0.48 Hz). This is satisfied.
So rad/s and
Angle deficiency
| Factor | Angle at |
|---|---|
| zero at | |
| double pole at | |
| Plant total |
The compensator must add of phase lead.
Placing the zero and pole
Put the zero at (near , which reduces the pull of the double pole):
- angle of is
- the pole must give :
Gain
Check
- Characteristic equation has roots (designed) and (fast, negligible).
- Simulated step response (T = 0.1 s): settles within 5% in about 1.1 s, which meets s. The peak is about 1.36 at s. This overshoot is larger than alone predicts because of the closed-loop zeros at 0.8 and −1, which are usual for a type-2 loop.
- The acceleration constant is , so steady-state error is zero for step and ramp commands.
r -->(+)-->[D(z)]-->[ZOH]-->[0.02/s]-->[1/s]--+--> c
^- |
+-----------------[360]<-----------------+
Answer: , giving dominant poles (, rad/s, time constant 0.33 s).
- 2075 Bhadra · 4 marks
Discuss the situations where you prefer phase lag/lead controllers and PID controllers.
Answer
Lag/lead compensators and PID controllers both reshape the loop, but each fits a different situation.
Prefer a phase-lead compensator when
- the system is stable but has a poor transient response (low phase margin, large overshoot, slow rise);
- you need a higher bandwidth and faster response, and some extra noise sensitivity is acceptable;
- the plant has an integrator or a double integrator (e.g. satellite or position servo) that needs phase lead to stabilise it.
Prefer a phase-lag compensator when
- the transient response is already satisfactory but the steady-state error is too large (low , );
- low-frequency gain must be raised without changing the crossover frequency much;
- high-frequency noise must be attenuated, and a slower response is acceptable.
A lag–lead compensator is used when both the transient and the steady-state response must be improved.
Prefer a PID controller when
- the plant model is not accurately known and the controller must be tuned on site (Ziegler–Nichols rules, for example);
- zero steady-state error to a step is needed (integral action) together with damping (derivative action);
- the plant is a process plant (temperature, pressure, flow, level) with slow dynamics or dead time, where PID is the industry standard;
- the controller must be simple, with three parameters an operator can understand.
| Situation | Preferred controller |
|---|---|
| Good steady state, poor transient | Lead |
| Good transient, poor steady state | Lag |
| Both poor, model known | Lag–lead |
| Model unknown, tuning in field | PID |
| Process plants with dead time | PI / PID |
| Noisy measurement | Lag or PI (avoid D) |
- 2072 Asoj · 6 marks
Write down the general procedures for frequency response design in discrete time control system.
Answer
Frequency-response design of a discrete-time system is done in the w-plane. The bilinear transformation maps the unit circle of the z-plane onto the imaginary axis of the w-plane, so the usual Bode-diagram methods can be used.
Procedure
- Find the pulse transfer function of the plant with the zero-order hold: .
- Transform to the w-plane with the bilinear transformation: Write in time-constant form. The fictitious frequency () is related to the actual frequency by .
- Choose the controller gain to meet the static error constant (, or ), using in the w-plane, which gives the same constants as in the s-plane.
- Draw the Bode diagram of and read the uncompensated gain crossover frequency, phase margin and gain margin.
- Select the compensator :
- lead (): needed phase ; ; place at the new crossover where ; ;
- lag ( in this form): put the new crossover where the phase gives the required PM, and place the corner frequencies one decade below it.
- Check the compensated Bode diagram for phase margin, gain margin and bandwidth. Repeat step 5 if needed.
- Transform back to the z-plane with to get , which is then realised as a difference equation in the computer.
- Verify with the closed-loop step response (simulation), and check that the sampling period is small compared with the closed-loop bandwidth (8–10 samples per cycle).
G(s) --ZOH--> G(z) --bilinear--> G(w) --Bode--> GD(w)
|
GD(z) <---------- w = (2/T)(z-1)/(z+1) ----+
Points to remember
- The w-plane magnitude is not bounded at as in the s-plane: usually has a zero at (non-minimum phase), which adds lag at high frequency.
- Since for , the design reads like a continuous-time design when sampling is fast.
- 2072 Magh · 16 marks
Design a digital controller for the system shown below. Use the Bode diagram approach in s plane. The design specifications are that the phase margin be 55°, the gain margin be at least 10 dB and the static velocity error constant be 5 sec⁻¹. The sampling period is specified as 0.1 sec. [Figure: unity-feedback loop: R(z) → summing junction → sampler → digital controller → ZOH → plant 1/s(s+2) → C(z)]
Answer
The design is done in the w-plane (bilinear transformation), where the Bode diagram can be used as in the s-plane. A lead compensator is used.
Step 1: Pulse transfer function of the plant
With s and :
Step 2: Transform to the w-plane
Substitute :
Step 3: Gain for
Step 4: Uncompensated Bode data ()
| (rad/s) | 1 | 2 | 4 | 6 | 10 | 20 |
|---|---|---|---|---|---|---|
| Magnitude (dB) | 13.0 | 5.0 | −4.9 | −11.2 | −19.2 | −29.1 |
| Phase (deg) | −119.4 | −140.6 | −164.4 | −177.8 | −194.3 | −217.4 |
Gain crossover is at rad/s and the phase margin is only 26.8°. About 28° or more of lead is needed. The w-plane zero at adds extra lag at high frequency, so a larger lead is needed than in a continuous design.
Step 5: Lead compensator
Choose the compensator zero to cancel the plant pole at , so . Then reduce until PM = 55°:
| New crossover | PM | GM | |
|---|---|---|---|
| 0.25 | 4.47 | 48.6° | 12.3 dB |
| 0.20 | 4.65 | 52.3° | 12.3 dB |
| 0.17 | 4.76 | 55.0° | 12.3 dB |
Compensated loop: . Phase margin = 55°, phase crossover at rad/s, gain margin = 12.3 dB (≥ 10 dB).
Step 6: Back to the z-plane
Substitute :
Check of
Answer: , giving PM ≈ 55°, GM ≈ 12.3 dB and .
- 2071 Bhadra · 6 marks
Draw root locus plot for the given system below. [Figure: unity-feedback loop: R(s)=1/s → summing junction → sampler (T = 0.5 sec) → ZOH → 1/s(s+1) → C(s)]
Answer
The root locus is drawn in the z-plane for the open-loop pulse transfer function with gain K in the forward path.
Open-loop pulse transfer function
With s and :
- Open-loop poles: ,
- Open-loop zero: (the other branch ends at )
Construction
- Real-axis locus: between 0.6065 and 1, and to the left of −0.8467.
- Breakaway / break-in points from , where :
- Complex part: for one real zero and two real poles the complex part is a circle centred at the zero: centre , radius .
- Crossing of the unit circle: characteristic equation For complex roots , so . The roots are then (angle 55.2°, rad/s).
Sketch
Im
| . unit circle
. | x <- K=4.36, z=0.57+j0.82
. | .
o---------+----x--x---> Re
-2.48 -0.85| 0.61 | 1
break-in zero breakaway 0.79
. | .
. | x <- K=4.36
|
circle: centre -0.85, radius 1.64
Result
- For : two real closed-loop poles between 0.6065 and 1 (overdamped).
- For : complex poles on the circle. They lie inside the unit circle only while .
- The system is stable for ; at it oscillates at about 1.93 rad/s.
- The input does not change the locus; it only decides the step response.
- 2071 Bhadra · 5 marks
Explain how PID controller is realized in discrete time domain. Discuss the role of P, I and D parts.
Answer
A digital PID controller is obtained by replacing the integral and derivative of the analog PID law with sums and differences of the sampled error .
Analog PID law
Discretization
- Integral by the trapezoidal rule, derivative by the backward difference:
- Taking the z-transform:
Realization (velocity / recursive form)
Multiplying by gives an algorithm that needs only the last two errors and the last output:
+--> [ KP ] -----------------+
| v
e(k) ----+--> [ KI/(1-z^-1) ] ---->( + )---> m(k)
| ^
+--> [ KD(1-z^-1) ] ---------+
The computer runs this equation once every sampling period, and the D/A converter with a zero-order hold applies to the plant.
Role of each part
- P (proportional): gives an output proportional to the present error. A larger makes the response faster and reduces steady-state error, but too much gain causes overshoot and instability.
- I (integral): adds a pole at and accumulates past error. It removes steady-state error to a step (raises the system type by one) but adds phase lag, so it can make the response more oscillatory. Anti-windup is needed when the actuator saturates.
- D (derivative): responds to the rate of change of error, so it anticipates future error. It adds damping, reduces overshoot and improves stability, but it amplifies high-frequency measurement noise. It is often applied to the measured output instead of the error, with a filter.
- 2068 Magh · 16 marks
Design a digital controller for the system shown in figure below so that dominant closed loop poles of the system will have damping ratio of 0.5. It is required that the peak time of the response tₚ≤ 1.2 sec. Assume sampling time T = 0.2 sec. [Figure: unity-feedback loop: R(z) → summing junction → sampler → digital controller → m*(kT) → ZOH → 1/s(s+1) → C(z)]
Answer
A lead-type digital controller is designed by the z-plane root-locus method. Its zero cancels the slow plant pole.
Plant pulse transfer function ( s)
With :
Desired dominant poles
That is 12 samples per cycle of damped oscillation, which is adequate.
Angle deficiency
| Factor | Angle at |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The controller must add .
Controller zero and pole
- Zero at cancels the plant pole and removes its .
- Then the controller pole must give , so :
Gain
Check
- Characteristic equation: , roots , which is the design point.
- Step response: . The peak is 1.163 at s, so s is met.
- Velocity error constant:
Answer: , giving closed-loop poles (, s).
- 2068 Jestha · 16 marks
Consider the system shown below. Design a digital controller such that the dominant closed loop poles of the system will have damping ratio ζ of 0.55. It is required that the peak time of the response be 1.2 sec. Assume that the sampling period T be 0.2. Also obtain Kᵥ for the designed system. [Figure: unity-feedback loop: r(t)/R(z) → summing junction → sampler → digital controller → (1-e⁻ᵀˢ)/s → 1/s(s+1) → c(t)/C(z)]
Answer
A lead-type digital controller is designed by the root-locus method in the z-plane. Its zero cancels the plant pole at .
Plant pulse transfer function ( s)
Desired dominant poles
Angle condition
| Factor | Angle at |
|---|---|
| zero at | |
| pole at | |
| pole at | |
| Total |
The angle deficiency is , so lead compensation is needed.
- Place the controller zero at to cancel the plant pole.
- The controller pole angle must be :
Gain from the magnitude condition
Check
- Closed-loop characteristic equation: , roots .
- Step response peak at , i.e. s.
Velocity error constant
So the steady-state error to a unit ramp is .
Answer: ; .
- 2067 Mangsir · 16 marks
Consider the system shown below. Design a digital PI controller such that the dominant closed loop poles have a damping ratio of 0.55 and number of samples per cycle of damped oscillation is 10. Also find Kᵥ for the designed system. [Figure: unity-feedback loop: R(z) → summing junction → sampler → GD(z) → (1-e⁻ᵀˢ)/s → e⁻²ˢ/(s+2) → C(z)]
Answer
A digital PI controller is designed with the root-locus angle and magnitude conditions. The sampling period is not given; s is assumed. It makes the 2 s dead time exactly two samples and allows a feasible PI design.
Plant pulse transfer function
With :
Desired dominant poles
10 samples per cycle gives :
Angle condition
| Pole | Angle at |
|---|---|
| double pole at 0 | |
| pole at 0.1353 | |
| PI pole at 1 | |
| Total |
The PI zero must contribute :
Magnitude condition
So and .
Check
Characteristic equation: , with roots (designed), and . Step response: . The peak is about 2% and there is zero steady-state error.
Velocity error constant
The steady-state error to a unit ramp is .
Answer: (, , with T = 1 s); .
- 2068 Magh · 4 marks
Write a short note on phase-lead/phase-lag compensator.
Answer
A compensator is an extra block placed in the loop to change the root locus or the frequency response so that the specifications are met. Its digital form is
Phase-lead compensator
- The zero is nearer to than the pole (), so it gives positive phase, at most where (w-plane form , ).
- It moves the root locus to the left (towards the origin of the z-plane), so it increases phase margin, damping and bandwidth.
- Result: faster response and less overshoot, but more high-frequency noise.
Phase-lag compensator
- The pole is nearer to than the zero (), both close to 1. It gives negative phase but high low-frequency gain.
- It raises the static error constants (, ) by about without much change to the transient response.
- Result: lower steady-state error and less noise, but a slower response.
| Feature | Lead | Lag |
|---|---|---|
| Phase added | Positive | Negative |
| Main effect | Transient response | Steady-state error |
| Bandwidth | Increases | Decreases |
| Noise | Amplified | Attenuated |
| Pole–zero order | Zero closer to z=1 | Pole closer to z=1 |
A lag–lead compensator combines the two when both transient and steady-state performance must be improved.
- 2068 Magh · 4 marks
Write a short note on advantage of digital filter.
Answer
A digital filter is a filter carried out as a difference equation on sampled data in a processor, e.g. . In control systems the digital controller itself is a digital filter.
Advantages
- Flexibility: the characteristics are changed by editing coefficients or software, with no rewiring.
- No drift: performance does not change with temperature, ageing or component tolerance, unlike R, L, C and op-amp circuits.
- Accuracy and repeatability: set by word length; every unit built behaves identically.
- Complex and adaptive filters: linear phase (FIR), very sharp cut-offs, notch filters and adaptive or time-varying filters are easy to build.
- Very low frequencies can be handled without the huge capacitors an analog filter would need.
- Multiplexing: one processor can filter many channels.
- Storage and integration: data can be stored, and filtering, control, logging and communication run in the same computer.
- No impedance-matching or loading problems between stages.
Limitations
Sampling and quantization errors, aliasing (an anti-aliasing analog filter is still needed), a limited bandwidth set by the sampling rate, and a computation delay.
Questions from Old Question Collection (EE 652) (NCE Library scans of IOE Digital Control System papers, 2067 Mangsir to 2082 Chaitra), 2080 course papers (ENEE 304) (New-course (ENEE 304) regular paper, 2082 Chaitra) and Question bank (ioesolutions) (IOE Digital Control System papers, 2067 Mangsir to 2075 Baisakh; used for the second pages of the 2068 Magh and 2068 Jestha papers). Answers are written for this site; check them against your class notes.
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