Introduction to Discrete Time Control System

A discrete time (digital) control system takes analog signals from the plant, converts them to numbers (data acquisition and conversion), processes them in a computer, and sends the result back to the plant as analog signals (data distribution).

Block diagram

 DATA ACQUISITION
 Sensor -> Amp -> LPF --+
 Sensor -> Amp -> LPF --+--> Analog --> S/H --> A/D
 Sensor -> Amp -> LPF --+     MUX                |
                                                 v
                                              Digital
                                              computer
 DATA DISTRIBUTION                               |
 Actuator <- Hold <--+                           v
 Actuator <- Hold <--+-- Demux <-- D/A <-- Register

Data acquisition

The data acquisition system collects analog signals from many points of the plant and prepares them for conversion.

1. Transducer/sensor: converts the physical variable (temperature, speed, pressure, position) into a voltage or current.
2. Amplifier: raises the low-level sensor signal to the range of the A/D converter (e.g. 0 to 10 V) and gives isolation.
3. Low-pass (anti-aliasing) filter: removes high-frequency noise so that the signal is band-limited below half the sampling frequency, avoiding aliasing.
4. Analog multiplexer: a set of electronic switches that connects one of many analog channels at a time to the single S/H and A/D, so one converter serves many inputs (time sharing).

Data conversion

5. Sample-and-hold (S/H): takes the sample of the selected signal at the sampling instant and holds it constant while conversion takes place.
6. A/D converter: quantizes the held voltage and codes it into an n-bit binary number. The computer reads this number.
7. Digital computer/controller: compares the measured values with the set points and computes the control action $u(kT)$ using the control algorithm (PID, lead/lag, state feedback).

Data distribution

8. Register/D/A converter: the output word is latched in a register and converted into an analog voltage by the D/A converter.
9. Demultiplexer: routes the D/A output to the correct output channel; a single D/A can serve many actuators.
10. Hold circuit (ZOH): keeps each channel's output constant between updates, producing a staircase signal.
11. Actuator: (motor, valve, heater driver) applies the control action to the plant.

Timing

A clock (timer) gives the sampling period $T$. In each period the computer selects a channel, samples, converts, computes, and updates the outputs. The whole cycle must finish within $T$.

Example: in a boiler, temperature, pressure and level sensors feed one multiplexer and one 12-bit ADC; the computer computes valve openings and sends them through a D/A converter and demultiplexer to the fuel and feed-water valves.

A digital control system is a feedback control system in which a digital computer (microprocessor, microcontroller or PLC) acts as the controller. The plant is continuous, so signals are converted between analog and digital forms at the controller's input and output.

Block diagram

 r(kT) -->(+)--> Digital  --> D/A --> Hold
           ^ -   computer             (ZOH)
           |                            |
           |                            v
          A/D                       Actuator
           ^                            |
           |                            v
          S/H                         Plant ---> y(t)
           ^                            |
           +-------- Sensor <-----------+

Function of each block

Working

1. The output $y(t)$ is measured by the sensor and gives an analog signal.
2. The S/H samples it at $t = kT$ and the A/D converts it into a digital number $y(kT)$.
3. The computer forms the error $e(kT) = r(kT) - y(kT)$ and solves a difference equation, for example the PID law $u(kT) = K_p e(kT) + K_i \sum e(iT) + K_d [e(kT)-e((k-1)T)]$.
4. The D/A converter and ZOH turn $u(kT)$ into a piecewise-constant analog signal $u(t)$.
5. The actuator applies $u(t)$ to the plant, and the cycle repeats every sampling period.

Types of signals in the loop

• Continuous-time analog: plant output, actuator input.
• Sampled-data (discrete-time analog): S/H output.
• Digital (quantized and coded): inside the computer.

Main features

• The controller is a program, so the control law can be changed easily.
• One computer can handle many loops by multiplexing.
• The sampling period $T$ must be small compared with the plant time constants (normally 8 to 10 samples per cycle of the damped oscillation) to give good performance.
• Quantization and sampling introduce small errors and delays that must be considered in design.

Example: in a DC motor speed control, a tachogenerator measures speed, a microcontroller with built-in ADC runs a PI algorithm, and a PWM output (acting as D/A plus hold) drives the motor through a power amplifier.

A zero order hold (ZOH) holds each sample value constant until the next sample arrives. Its output is a staircase signal. Its transfer function is found from its impulse response.

Impulse response

Apply a unit impulse $\delta(t)$ (sample of strength 1 at $t=0$). The ZOH holds this value for one sampling period $T$ and then drops to zero:

$$g_{h0}(t) = \begin{cases} 1, & 0 \le t < T \\ 0, & \text{otherwise} \end{cases}$$

 g(t)
  1 |------+
    |      |
    |      |
  0 +------+---------> t
    0      T

This rectangular pulse is the difference of two unit steps:

$$g_{h0}(t) = u(t) - u(t-T)$$

Laplace transform

Using $\mathcal{L}[u(t)] = \frac{1}{s}$ and the time-shift theorem $\mathcal{L}[f(t-T)u(t-T)] = e^{-Ts}F(s)$:

$$\begin{aligned} G_{h0}(s) &= \mathcal{L}[u(t)] - \mathcal{L}[u(t-T)] \\ &= \frac{1}{s} - \frac{e^{-Ts}}{s} \\ &= \frac{1-e^{-Ts}}{s} \end{aligned}$$

which is the required result.

General input

For an impulse-sampled input $x^*(t) = \sum x(kT)\delta(t-kT)$, the output is $h(t) = \sum_k x(kT)[u(t-kT) - u(t-(k+1)T)]$, whose Laplace transform is $X^*(s)\,\frac{1-e^{-Ts}}{s}$, confirming the same transfer function.

Frequency response (for reference)

Putting $s = j\omega$: $G_{h0}(j\omega) = T\,\frac{\sin(\omega T/2)}{\omega T/2}\,e^{-j\omega T/2}$, so the ZOH is a low-pass filter with a phase lag of $\omega T/2$ (a delay of half a sampling period).

A digital control system is a closed-loop system in which a digital computer acts as the controller. The plant is analog, so the system contains A/D and D/A interfaces, and the controller works only at sampling instants $t = kT$.

Block diagram

 r(kT) -->(+)--> Digital  --> D/A --> Hold
           ^ -   computer             (ZOH)
           |                            |
           |                            v
          A/D                       Actuator
           ^                            |
           |                            v
          S/H                         Plant ---> y(t)
           ^                            |
           +-------- Sensor <-----------+

Explanation of blocks

1. Sensor (transducer): measures the controlled variable (speed, temperature) and gives an analog voltage.
2. Sample-and-hold (S/H): samples the sensor signal every $T$ seconds and holds the value steady while it is converted.
3. A/D converter: quantizes the held value into one of $2^n$ levels and codes it as an n-bit binary word.
4. Digital computer: reads the digital value, compares it with the reference $r(kT)$ and computes the control output $u(kT)$ from a difference equation (e.g. PID or lead compensator).
5. D/A converter: converts the binary output into an analog voltage.
6. Hold circuit (ZOH): keeps the D/A output constant between updates, giving a staircase signal $u(t)$.
7. Actuator: power amplifier, motor or valve that applies the control effort to the plant.
8. Plant: the continuous process whose output $y(t)$ is controlled.
9. Clock: generates the sampling instants and keeps S/H, A/D, computer and D/A in step.

Operation

Every sampling period: sample, convert, compute, output, hold. Between samples the plant runs open-loop with the held input. If the sampling period is small compared with the plant's time constants (8 to 10 samples per cycle of oscillation), the system behaves almost like a continuous one.

Signal types in the loop

• Continuous analog: $y(t)$, $u(t)$.
• Sampled (discrete-time) analog: S/H output.
• Digital (quantized and coded): inside the computer.

Advantages of digital control over analog control

• Flexibility: the control law is software; it can be changed (P to PID, new gains) without rewiring hardware.
• Accuracy and repeatability: digital values do not drift with temperature, ageing or component tolerance.
• Noise immunity: binary signals are far less affected by noise and interference than analog voltages.
• Complex control laws: nonlinear, adaptive, optimal and self-tuning control are easy to code but very hard to build with op-amps.
• Time sharing: one computer can control many loops through multiplexing, reducing cost per loop.
• Data handling: easy storage, logging, display, alarms and communication over networks (SCADA, DCS).
• Lower cost and size: cheap microcontrollers replace bulky analog hardware.
• Reliability and diagnostics: self-checking and fault detection are built into software.

Limitations (for balance)

• Sampling and the ZOH add phase lag, which can reduce stability if $T$ is large.
• Quantization adds a small error (noise).
• Needs A/D and D/A interfaces and software design effort.

Example: a CNC machine tool uses a microcontroller to read encoders, run a PID position loop at 1 kHz, and drive the axis motors through PWM amplifiers.

A digital control system uses a computer or microcontroller as the controller. Compared with an analog (op-amp/RC) controller it has these advantages:

1. Flexibility: the control law is a program. Gains or the whole algorithm can be changed by software, without changing hardware.
2. Accuracy and stability of parameters: digital values do not drift with temperature, ageing or component tolerance, so performance stays repeatable.
3. Noise immunity: binary signals are much less affected by noise and interference than low-level analog voltages.
4. Complex control: nonlinear, adaptive, optimal, self-tuning and logic-based control are easy to code but hard or impossible with analog circuits.
5. Time sharing: one processor can control many loops through multiplexing, lowering cost per loop.
6. Data storage and communication: values can be logged, displayed, trended and sent over networks (SCADA, IoT); supervisory control is easy.
7. Cost, size and weight: cheap microcontrollers replace bulky analog hardware.
8. Reliability and diagnostics: self-tests, alarms and fault detection can be built into the software.
9. Wide dynamic range: limited only by word length, not by supply voltage.

Example: changing a furnace controller from PI to PID needs only new code and new gains in a digital controller, but needs new components and recalibration in an analog one.

A sample-and-hold (S/H) circuit takes the value of an analog signal at a sampling instant and holds it constant for the time needed by the A/D converter to convert it. Without S/H, the input could change during conversion and give a wrong digital output.

Circuit

            Switch S
 Vin --[Buf A1]--o/ o--+--[Buf A2]--> Vout
                       |
                      === C (hold capacitor)
                       |
                      GND
       Control (sample/hold) drives switch S

• A1: input buffer with low output impedance, so C charges quickly.
• S: electronic switch (FET/MOSFET) driven by the control (logic) signal.
• C: hold capacitor that stores the voltage.
• A2: output buffer with very high input impedance, so C does not discharge.

Tracking (sample) mode

• The control signal closes the switch.
• C charges through A1, and the output follows (tracks) the input: $V_{out}(t) \approx V_{in}(t)$.
• The time needed for the output to reach the input within the stated accuracy is the acquisition time.

Hold mode

• The control signal opens the switch at the sampling instant.
• C keeps the voltage it had at that instant. A2 draws almost no current, so $V_{out}$ stays constant.
• The A/D converter converts this steady voltage during the hold period.

 Vin   /\    /\
      /  \  /  \
 Vout __|‾‾|__|‾‾|__   (track | hold | track | hold)
 Ctrl  T  H  T  H

Use in digital control

1. At each sampling instant $kT$ the controller switches the S/H to hold, and starts the ADC.
2. After conversion it returns the S/H to track mode to follow the signal until the next instant.
3. In a multichannel data acquisition system one S/H after the multiplexer holds each channel in turn; at the output, hold circuits (ZOH) keep each D/A output constant between updates.

Important non-ideal terms

• Aperture time: delay between the hold command and the switch actually opening.
• Droop: slow fall of the held voltage due to leakage current, $dV/dt = I_{leak}/C$.
• Feedthrough: small part of the input appearing at the output during hold.

Mathematically, the S/H acts as an ideal sampler followed by a zero order hold, $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$.

Sampling converts a continuous-time signal into a sequence of values (pulses) taken at certain instants. Sampling operations are classified by how the sampling instants are chosen.

Types

1. Periodic (conventional) sampling: samples taken at equal intervals $t = kT$. Most common; gives simple difference equations and the z-transform.
2. Multiple-order sampling: the pattern of sampling instants repeats periodically, i.e. $t_{k+r} - t_k$ is constant, but spacing within a pattern is not equal.
3. Multiple-rate sampling: different loops or signals are sampled at different periods, e.g. a fast inner current loop and a slow outer speed loop.
4. Random sampling: instants are random, e.g. event-driven systems or networked control with random delays. Hard to analyse.

Comparison

Sampling by pulse shape (also asked)

In digital control, periodic flat-top sampling (S/H) is used in practice, and it is modelled as ideal impulse sampling followed by a zero order hold.

A first order hold (FOH) reconstructs the signal between samples by a straight line extrapolated from the last two samples:

$$h(kT+\tau) = x(kT) + \frac{x(kT) - x((k-1)T)}{T}\,\tau, \qquad 0 \le \tau < T$$

Impulse response

Apply a unit impulse at $t=0$, so $x(0)=1$ and all other samples are zero.

• For $0 \le t < T$ ($k=0$): $h = 1 + \frac{1-0}{T}t = 1 + \frac{t}{T}$ (rises from 1 to 2).
• For $T \le t < 2T$ ($k=1$, $x(T)=0$, $x(0)=1$): $h = 0 + \frac{0-1}{T}(t-T) = -\frac{t-T}{T}$ (from 0 to -1).
• For $t \ge 2T$: $h = 0$.

 g(t)
  2 |     /|
    |   /  |
  1 | /    |
  0 +------+------+----> t
    0      T \    | 2T
 -1 |         \---|

Writing it with steps and ramps

$$\begin{aligned} g_{h1}(t) &= u(t) + \frac{t}{T}u(t) - 2u(t-T) - \frac{2(t-T)}{T}u(t-T) \\ &\quad + u(t-2T) + \frac{t-2T}{T}u(t-2T) \end{aligned}$$

Check: for $0\le t<T$ it gives $1+t/T$; for $T\le t<2T$ it gives $1+\frac{t}{T}-2-\frac{2(t-T)}{T} = -\frac{t-T}{T}$; for $t\ge 2T$ it gives 0.

Laplace transform

Using $\mathcal{L}[u(t)]=\frac1s$, $\mathcal{L}[t\,u(t)]=\frac{1}{s^2}$ and the shift theorem:

$$\begin{aligned} G_{h1}(s) &= \frac1s + \frac{1}{Ts^2} - \frac{2e^{-Ts}}{s} - \frac{2e^{-Ts}}{Ts^2} + \frac{e^{-2Ts}}{s} + \frac{e^{-2Ts}}{Ts^2} \\ &= \left(\frac1s + \frac{1}{Ts^2}\right)\left(1 - 2e^{-Ts} + e^{-2Ts}\right) \\ &= \frac{Ts+1}{Ts^2}\,(1-e^{-Ts})^2 \\ &= \frac{Ts+1}{T}\left(\frac{1-e^{-Ts}}{s}\right)^2 \end{aligned}$$

which is the required transfer function of the first order hold.

Remarks

• The FOH follows ramps better than the ZOH, but it has more phase lag at higher frequencies and needs storage of the previous sample.
• Since $G_{h1}(s) = \frac{Ts+1}{T}\,G_{h0}^2(s)$, it can be seen as two ZOH blocks in cascade with a lead term $(Ts+1)/T$.

A sample-and-hold (S/H) circuit has an electronic switch, a hold capacitor $C$ and buffer amplifiers. It works in two modes set by a logic control signal.

 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C
                   |
                  GND

Tracking (sample) mode

• The switch is closed.
• The capacitor charges through the low-impedance input buffer and the output follows the input: $V_{out}(t) \approx V_{in}(t)$.
• The time taken for the output to settle to the input value is the acquisition time.

Hold mode

• The switch is opened at the sampling instant.
• The capacitor keeps the voltage it had at that instant, and the high-impedance output buffer prevents discharge, so $V_{out}$ stays constant at $V_{in}(kT)$.
• The A/D converter converts this constant voltage during the hold time.
• Small errors in this mode: droop (slow fall of voltage due to leakage) and feedthrough.

A data acquisition system (DAS) is the part of a digital control system that collects analog signals from sensors at many points of a plant, conditions them, and converts them into digital numbers that the computer can read.

Block diagram

 Sensor1 -> Amp -> LPF --+
 Sensor2 -> Amp -> LPF --+--> Analog -> S/H -> A/D -> CPU
 Sensor3 -> Amp -> LPF --+     MUX      ^      ^
                                |       |      |
                                +-------+------+
                                |
                         Control logic / clock

Blocks

1. Transducers (sensors): convert physical quantities (temperature, pressure, flow, speed, position) into electrical signals. Examples: thermocouple, strain gauge, tachogenerator, encoder.
2. Signal conditioning amplifier: amplifies the small sensor signal (millivolts) to the full-scale range of the ADC, gives high input impedance, isolation and common-mode rejection (instrumentation amplifier).
3. Low-pass (anti-aliasing) filter: removes high-frequency noise and limits the signal bandwidth to below $\omega_s/2$ so that aliasing does not occur.
4. Analog multiplexer: a set of electronic switches that connects the channels one at a time to the single S/H and ADC. This time-sharing lowers cost.
5. Sample-and-hold circuit: samples the selected channel at the sampling instant and holds the value constant while it is converted.
6. A/D converter: quantizes the held voltage into one of $2^n$ levels and codes it as an n-bit binary word (successive approximation, dual slope, flash).
7. Control logic/clock: selects the multiplexer channel, issues sample/hold and start-of-conversion commands, and signals the computer at end of conversion.
8. Computer interface: the digital word is read through a port or bus and stored for processing.

Operation

The controller selects channel 1, the S/H samples it, the ADC converts it, and the result is stored; then channel 2 is selected, and so on. All channels are scanned within one sampling period $T$.

Example: in a power substation, voltage, current and temperature transducers feed a multiplexed 12-bit ADC whose output is sent to a SCADA computer.

Impulse sampling is the ideal mathematical model of sampling in which the sampler output is a train of impulses at $t = kT$, each with strength (area) equal to the signal value at that instant. Real samplers give narrow pulses, but when the pulse width is very small compared with $T$ (and a hold follows) they can be modelled this way.

Diagram

 x(t) ---->o/o----> x*(t)
          T (sampler)

 x(t)            x*(t)
   /‾‾\            |  |
  /    \          ||  ||
 /      \__      |||  |||_
 ---------> t    -+-+-+-+-+--> t
                 0 T 2T 3T

Derivation

The ideal sampler multiplies the input by a unit impulse train:

$$\delta_T(t) = \sum_{k=0}^{\infty} \delta(t-kT)$$ $$\begin{aligned} x^*(t) &= x(t)\,\delta_T(t) = \sum_{k=0}^{\infty} x(t)\,\delta(t-kT) \\ &= \sum_{k=0}^{\infty} x(kT)\,\delta(t-kT) \end{aligned}$$

(using $x(t)\delta(t-kT) = x(kT)\delta(t-kT)$, with $x(t)=0$ for $t<0$).

Taking the Laplace transform, $\mathcal{L}[\delta(t-kT)] = e^{-kTs}$:

$$X^*(s) = \sum_{k=0}^{\infty} x(kT)\,e^{-kTs}$$

Putting $z = e^{Ts}$ gives the z-transform:

$$X(z) = X^*(s)\Big|_{s=\frac1T\ln z} = \sum_{k=0}^{\infty} x(kT)\,z^{-k}$$

Frequency-domain form

Expanding $\delta_T(t)$ as a Fourier series gives

$$X^*(s) = \frac{1}{T}\sum_{n=-\infty}^{\infty} X(s + jn\omega_s), \qquad \omega_s = \frac{2\pi}{T}$$

so the spectrum of the sampled signal is the original spectrum repeated every $\omega_s$. This leads to the sampling theorem $\omega_s > 2\omega_m$.

To convince the board, the case should be presented in terms of cost, production, quality and risk, supported by data from the plant.

1. Present problems with the existing analog system

• Drift and frequent recalibration of analog controllers; old parts hard to find.
• No record of process data, so faults and quality losses are hard to trace.
• Each loop needs its own controller and panel space.

2. Benefits of digital control

• Better product quality: accurate, repeatable control with no drift; less scrap and rework.
• Higher productivity: advanced control (cascade, feed-forward, adaptive) gives faster start-up and less downtime.
• Flexibility: recipes, set points and control laws changed by software for new products, without new hardware.
• Lower cost per loop: one PLC/DCS handles many loops; less wiring and panel space.
• Data and monitoring: logging, trends, alarms, remote monitoring (SCADA), and energy reporting.
• Predictive maintenance and diagnostics: fewer unplanned shutdowns.
• Safety: interlocks and emergency shutdown logic in software.
• Future readiness: integration with ERP, Industry 4.0 and IoT.

3. Financial justification

• Give the capital cost (hardware, software, installation, training).
• Estimate yearly savings (energy, scrap, labour, maintenance, downtime).
• Show the payback period and return on investment, e.g. a cost of Rs 50 lakh saving Rs 20 lakh a year pays back in 2.5 years.

4. Plan to manage risk

• Pilot project on one line before full roll-out.
• Phased change-over during planned shutdowns; keep manual back-up.
• Train operators and maintenance staff; choose a vendor with local support.

A short presentation with these points, supported by figures from a pilot study, makes a strong case.

A sample-and-hold (S/H) circuit samples an analog signal at a given instant and holds that value constant for a fixed time, so that an A/D converter can convert a steady input.

Circuit

           Switch S (MOSFET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
      Logic control signal --> gate of S

• A1: input buffer (voltage follower) with very low output impedance.
• S: electronic switch controlled by the sample/hold logic signal.
• C: low-leakage hold capacitor (polystyrene/Teflon).
• A2: output buffer (voltage follower) with very high input impedance.

Sample (track) mode: S closed; C charges quickly through A1, and $V_{out}$ follows $V_{in}$. Hold mode: S open; C stores the voltage at the instant of opening.

How the voltage stays constant when the switch is open

The voltage across a capacitor changes only if current flows: $\frac{dV_C}{dt} = \frac{i}{C}$. When the switch is open, the circuit is designed so that $i \approx 0$:

1. Open switch: an OFF MOSFET has extremely high resistance, so no charge flows back to the input.
2. High-impedance output buffer: A2 (FET-input op-amp) draws only picoamperes, so the capacitor is not loaded.
3. Low-leakage capacitor: dielectric with very high insulation resistance.
4. Suitable C value: a larger C reduces droop rate.

Since $Q = CV$ is trapped on the capacitor, $V_C$ stays almost constant. A small fall called droop remains:

$$\frac{dV}{dt} = \frac{I_{leak}}{C}$$

Example: $I_{leak} = 1$ nA, $C = 1$ nF gives droop $= 1$ V/s, i.e. only 10 µV in a 10 µs conversion time.

Trade-off: large C means low droop but longer acquisition time in sample mode.

Advantages of digital control system over analog

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

Data acquisition system in DCS

The data acquisition system collects analog signals from plant sensors, conditions them, and converts them into digital form for the computer.

 Sensor -> Amp -> LPF --+
 Sensor -> Amp -> LPF --+--> Analog -> S/H -> A/D -> CPU
 Sensor -> Amp -> LPF --+     MUX

1. Transducer: converts the physical variable (temperature, speed, level) into a voltage or current.
2. Amplifier (signal conditioning): scales the small signal to the ADC input range and gives isolation.
3. Low-pass (anti-aliasing) filter: removes noise and limits bandwidth below half the sampling frequency.
4. Analog multiplexer: connects many channels, one at a time, to a single S/H and ADC (time sharing).
5. Sample-and-hold: captures the selected signal at the sampling instant and holds it during conversion.
6. A/D converter: quantizes and codes the held voltage into an n-bit binary number.
7. Control logic: selects channels and starts conversions at each sampling instant; the computer reads the result.

All channels are scanned once in every sampling period $T$. The data are then processed by the control algorithm, and the outputs are sent to actuators through D/A converters and hold circuits (data distribution).

Tracking mode and hold mode in S/H

 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C
                   |
                  GND

Tracking (sample) mode: the electronic switch is closed. The capacitor charges through the low-impedance buffer A1, and the output follows the input, $V_{out}(t) \approx V_{in}(t)$. The time to settle to the input within the required accuracy is the acquisition time.

Hold mode: the switch is opened at the sampling instant. The capacitor keeps its charge because the switch and the high-impedance buffer A2 draw almost no current, so $V_{out}$ stays at $V_{in}(kT)$. The ADC converts this steady value. A slow fall due to leakage is called droop.

Digital control system

A digital control system is a feedback system whose controller is a digital computer. Since the plant is analog, it needs A/D conversion at the controller input and D/A conversion at the output.

 r(kT) -->(+)--> Digital  --> D/A --> Hold
           ^ -   computer             (ZOH)
           |                            |
           |                            v
          A/D                       Actuator
           ^                            |
           |                            v
          S/H                         Plant ---> y(t)
           ^                            |
           +-------- Sensor <-----------+

1. Sensor: measures the plant output $y(t)$ as an analog signal.
2. Sample-and-hold: samples the signal every $T$ s and holds it during conversion.
3. A/D converter: quantizes and codes the sample into a binary word.
4. Digital computer: compares with the reference and computes $u(kT)$ by a control algorithm (PID, lead/lag, state feedback) written as a difference equation.
5. D/A converter: converts $u(kT)$ into an analog voltage.
6. Hold (ZOH): holds this voltage constant until the next update (staircase output).
7. Actuator and plant: the actuator applies the control effort to the plant.
8. Clock: sets the sampling period and synchronises all blocks.

In each period the loop does: sample, convert, compute, output, hold. With a small enough $T$ (8 to 10 samples per cycle of oscillation) the system behaves nearly like a continuous one.

Tracking mode and hold mode in S/H

 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C
                   |
                  GND

• Tracking mode: the switch is closed; C charges through A1 and the output follows the input.
• Hold mode: the switch is opened at the sampling instant; C keeps its voltage because the open switch and high-impedance buffer A2 draw almost no current, so the output stays at $V_{in}(kT)$ while the ADC converts it.

Control circuit of S/H

The switch is a MOSFET/JFET whose gate is driven by a logic control signal from the controller's timing unit:

• Control = 1 (sample): switch ON, tracking.
• Control = 0 (hold): switch OFF, holding.
• The hold command is given at each sampling instant just before the ADC's start-of-conversion pulse; after end-of-conversion the circuit returns to tracking.

 Control  ‾‾‾|____|‾‾‾‾|____|‾‾‾
           track hold track hold

Important timing terms: aperture time (delay between hold command and switch opening), acquisition time, and droop rate $I_{leak}/C$ during hold.

Data acquisition system

A data acquisition system collects analog signals from sensors in the plant, conditions them and converts them into digital numbers that the computer can process.

 Sensor1 -> Amp -> LPF --+
 Sensor2 -> Amp -> LPF --+--> Analog -> S/H -> A/D -> CPU
 Sensor3 -> Amp -> LPF --+     MUX      ^      ^
                                |       |      |
                                +-------+------+
                                |
                         Timing and control

1. Transducers: convert physical quantities (temperature, pressure, speed) into electrical signals.
2. Amplifier/signal conditioner: raises millivolt-level signals to the ADC range, provides isolation and rejects common-mode noise.
3. Low-pass (anti-aliasing) filter: removes high-frequency noise and limits the bandwidth below $\omega_s/2$.
4. Analog multiplexer: connects the channels one by one to a single S/H and ADC, so one converter serves many inputs.
5. Sample-and-hold: samples the selected signal at the sampling instant and keeps it steady during conversion.
6. A/D converter: quantizes and codes the value into an n-bit word.
7. Timing and control: selects the channel, gives sample/hold and start-of-conversion commands, and tells the computer when data are ready.

Operation: in every sampling period the channels are scanned in turn; each is sampled, held, converted and stored in memory. The computer then runs the control algorithm.

Example: a water treatment plant scans pH, turbidity and flow sensors through one 12-bit multiplexed ADC every second.

Advantages of digital control system

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

An analog-to-digital converter changes a continuous signal into binary numbers in several steps, and a decoder (D/A) changes them back.

 x(t) -> Sampler -> Hold -> Quantizer -> Encoder -> binary
                                                    word

Terms

• Sampling: taking the value of the continuous signal only at discrete instants $t = kT$ ($T$ = sampling period). The output is a discrete-time signal $x(kT)$ of continuous amplitude.
• Holding: keeping the sampled value constant for the conversion time (or until the next sample) by a sample-and-hold or zero order hold circuit, so the converter sees a steady input.
• Quantizing: rounding (or truncating) the held amplitude to the nearest of a finite set of levels. For an n-bit ADC with full-scale range $FSR$, there are $2^n$ levels and the step size is $Q = FSR/2^n$. The difference between true and quantized value is the quantization error, at most $\pm Q/2$.
• Coding (encoding): assigning a binary code (straight binary, BCD, two's complement, Gray) to each quantized level, giving an n-bit word. Example: 3-bit ADC, $FSR = 8$ V, input 5.3 V is quantized to level 5, coded as 101.
• Decoding: the reverse process in a D/A converter: converting the binary word back into an analog voltage, $V = Q \times (\text{decimal value of code})$. With a hold circuit this gives a staircase signal.

Advantages of digital control system over analog

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

In a digital control system the signal changes its form as it goes around the loop.

 y(t) -> S/H -> A/D -> CPU -> D/A -> Hold -> Plant
 (a)     (b)    (d)    (d)    (d)    (c)     (a)

Types of signals

1. Continuous-time analog signal (a): defined at every instant and can take any amplitude. Examples: plant output $y(t)$, actuator input.
2. Discrete-time analog (sampled-data) signal (b): defined only at sampling instants $kT$, but amplitude still continuous. Example: output of the sampler/S/H.
3. Continuous-time quantized signal (c): defined at all times but takes only certain amplitude levels. Example: staircase output of a D/A plus hold.
4. Digital signal (d): both discrete in time and quantized in amplitude, and coded in binary. Example: numbers inside the computer and the ADC output.

Signals of type (b) and (d) are both called discrete-time signals; systems containing them are discrete-time control systems.

Advantages of digital control system over analog

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

Sampling converts a continuous signal into a sequence of values taken at certain instants. Sampling operations differ in how the instants are chosen.

Types of sampling operation

1. Periodic (conventional) sampling: sampling instants equally spaced, $t_k = kT$. Most common; analysed with the z-transform.
2. Multiple-order sampling: the pattern of sampling instants is repeated periodically, i.e. $t_{k+r} - t_k$ is constant for all $k$, though spacing inside the pattern is unequal.
3. Multiple-rate sampling: two or more different sampling periods are used in one system, e.g. fast sampling for an inner current loop and slow sampling for an outer temperature loop.
4. Random sampling: instants are random, e.g. event-triggered or network-based control.

Comparison

By pulse shape, sampling may also be ideal (impulse), natural (pulse top follows the signal) or flat-top (S/H). Practical controllers use periodic flat-top sampling, modelled as an ideal sampler followed by a ZOH.

Advantages of digital control system over analog

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

Quantization is the rounding of a sampled amplitude to one of a finite number of levels in an A/D converter. For an n-bit ADC with full-scale range $FSR$, the step (quantum) is $Q = FSR/2^n$.

Problems caused by quantization

1. Quantization error: the difference between true and quantized value; with rounding it lies between $-Q/2$ and $+Q/2$.
2. Quantization noise: the error behaves like random noise of variance $Q^2/12$, which reduces signal-to-noise ratio.
3. Loss of small signals: changes smaller than $Q$ are not detected (dead zone).
4. Limit cycles: in a feedback loop the nonlinearity can cause small sustained oscillations of the output.
5. Steady-state error: the output can settle anywhere within one step of the set point.
6. Coefficient and arithmetic round-off in the controller with short word length.

Ways to improve

• Increase the number of bits (e.g. 8 to 12 bits): $Q$ falls by 16 times; SNR rises about 6 dB per bit.
• Match signal range to ADC range by proper amplification so all levels are used.
• Use rounding instead of truncation to make the error zero-mean.
• Oversampling and averaging/filtering to reduce noise.
• Dithering: add small noise before quantizing to break limit cycles.
• Longer word length and careful scaling in the controller software.

Problems associated with quantization

Quantization rounds each sampled value to one of $2^n$ levels of an n-bit A/D converter. The step size is $Q = FSR/2^n$.

1. Quantization error: the difference between true and quantized value, between $-Q/2$ and $+Q/2$ with rounding.
2. Quantization noise: the error acts like random noise with variance $Q^2/12$, lowering signal-to-noise ratio.
3. Loss of resolution: changes smaller than one step are not seen (dead zone).
4. Limit cycles: small sustained oscillations in closed loop due to the nonlinear staircase.
5. Steady-state error of up to one quantization step.
6. Round-off of coefficients and arithmetic in a short-word-length controller.

Example: a 4-bit ADC with 0 to 16 V has $Q = 1$ V; 6.4 V and 6.3 V both read 6 V, with error up to 0.5 V. An 8-bit ADC reduces $Q$ to 62.5 mV.

How it can be improved

• Use an ADC and processor with more bits (SNR improves about 6 dB per bit).
• Scale the signal to the full ADC range.
• Use rounding rather than truncation.
• Oversample and filter/average the readings.
• Add dither to break limit cycles.
• Use longer word length or floating point in the control algorithm.

Advantages of digital control system over analog

• Flexible: control law changed by reprogramming, not rewiring.
• Accurate and drift-free: no change with temperature or ageing of components.
• Better noise immunity of digital signals.
• Complex/adaptive/nonlinear control is easy to implement in software.
• One computer serves many loops (time sharing), so cost per loop is low.
• Easy data storage, display, alarms and networking.
• Smaller, cheaper, more reliable hardware.

Quantization in an A/D converter maps each sampled value to the nearest of $2^n$ discrete levels. The step size (quantum) is

$$Q = \frac{FSR}{2^n}$$

where $FSR$ is the full-scale range and $n$ the number of bits.

Quantization error

The difference between the actual sample and its quantized value:

$$e(kT) = x(kT) - x_q(kT)$$

With rounding, $-\frac{Q}{2} \le e \le \frac{Q}{2}$ (with truncation, $0 \le e < Q$). It is a fixed, bounded error for each sample.

Quantization noise

When the signal varies enough, the error changes randomly from sample to sample and can be treated as noise added to the signal: uniformly distributed over $\pm Q/2$, zero mean, with variance (noise power)

$$\sigma^2 = \frac{Q^2}{12}$$

The signal-to-quantization-noise ratio improves by about 6 dB for each extra bit.

Example

A 3-bit ADC with $FSR = 8$ V has $Q = 8/2^3 = 1$ V.

Noise power $= 1^2/12 = 0.0833\ \text{V}^2$ (rms $\approx 0.289$ V). Using an 8-bit ADC gives $Q = 31.25$ mV, so the error falls to at most $\pm 15.6$ mV.

Signal reconstruction is the process of recovering a continuous-time signal from its samples $x(kT)$, so that it can drive a continuous plant. In a digital control system it is done after the D/A converter by a hold circuit (signal reconstructor).

Ideal reconstruction

If the signal is band-limited and $\omega_s > 2\omega_m$, an ideal low-pass filter with cut-off $\omega_s/2$ recovers $x(t)$ exactly:

$$x(t) = \sum_{k=-\infty}^{\infty} x(kT)\,\frac{\sin[\omega_s(t-kT)/2]}{\omega_s(t-kT)/2}$$

This filter is non-causal (needs future samples), so it cannot be built.

Practical reconstructors (hold circuits)

A hold circuit extrapolates the signal between $kT$ and $(k+1)T$ from present and past samples using a polynomial:

$$h(kT+\tau) = a_n\tau^n + a_{n-1}\tau^{n-1} + \cdots + a_1\tau + a_0, \quad 0 \le \tau < T$$

with $h(kT) = x(kT)$, so $a_0 = x(kT)$. An $n$th-order hold uses the last $n+1$ samples.

• Zero order hold ($n=0$): $h(kT+\tau) = x(kT)$; staircase output. $G_{h0}(s) = \dfrac{1-e^{-Ts}}{s}$
• First order hold ($n=1$): straight-line extrapolation from two samples: $h(kT+\tau) = x(kT) + \dfrac{x(kT)-x((k-1)T)}{T}\,\tau$ $G_{h1}(s) = \dfrac{Ts+1}{T}\left(\dfrac{1-e^{-Ts}}{s}\right)^2$

 ZOH:  _|‾‾|__|‾‾‾|_   (steps)
 FOH:  /  /  /         (sloped segments)

The ZOH is the most used because it is simple and adds the least phase lag; higher-order holds give better tracking of smooth signals but more delay and complexity.

A sampled signal carries values only at $t = kT$. Reconstruction produces a continuous signal from these values, so that the output of a digital controller can drive an analog plant.

Spectrum of the sampled signal

The impulse-sampled signal has spectrum

$$X^*(j\omega) = \frac{1}{T}\sum_{n=-\infty}^{\infty} X(j(\omega + n\omega_s)), \quad \omega_s = \frac{2\pi}{T}$$

i.e. the original spectrum (primary component, $n=0$) plus copies (complementary components) centred at $\pm\omega_s, \pm 2\omega_s, \dots$

 |X*(jw)|
   _/\_      _/\_      _/\_
 --------+---------+---------> w
       -ws    0    ws
      copies  |  primary
         <-- ideal LPF -->
           -ws/2    ws/2

Condition for exact recovery

If $x(t)$ is band-limited to $\omega_m$ and $\omega_s > 2\omega_m$ (sampling theorem), the copies do not overlap. Then an ideal low-pass filter with gain $T$ and cut-off $\omega_s/2$ keeps only the primary component and gives back $x(t)$ exactly:

$$x(t) = \sum_{k} x(kT)\,\frac{\sin[\omega_s(t-kT)/2]}{\omega_s(t-kT)/2}$$

If $\omega_s < 2\omega_m$ the copies overlap (aliasing) and recovery is impossible.

Practical reconstruction

The ideal filter is non-causal, so practical systems use hold circuits, which build the signal from past samples only:

1. Zero order hold (ZOH): keeps $x(kT)$ constant until $(k+1)T$. Transfer function $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$. Its magnitude $T\left|\frac{\sin(\omega T/2)}{\omega T/2}\right|$ is a rough low-pass filter; it passes some high-frequency components (ripple) and adds a lag of $\omega T/2$.
2. First order hold (FOH): extrapolates with the slope of the last two samples. $G_{h1}(s) = \frac{Ts+1}{T}\left(\frac{1-e^{-Ts}}{s}\right)^2$.

 samples:   .   .   .
 ZOH:      |‾‾‾|‾‾‾|‾‾‾   staircase
 FOH:      /  /  /        ramps

Choosing a small $T$ (high sampling rate) and following the hold with a smoothing filter makes the reconstructed signal close to the original.

A sample-and-hold (S/H) circuit samples an analog signal at an instant and holds that value constant for a given time.

Why S/H is important

1. Steady input for the A/D converter: an ADC (e.g. successive approximation) needs several microseconds to convert. If the input changes during this time by more than half an LSB, the output code is wrong. The S/H freezes the input during conversion.
2. Allows fast signals to be converted: without S/H, a 12-bit ADC with 10 µs conversion time can only handle signals of a few hertz; with S/H, much higher frequencies.
3. Multiplexing: in a multichannel system one S/H and ADC serve many channels; the S/H keeps each sample while the multiplexer moves on.
4. Simultaneous sampling: several S/H circuits can capture many signals at the same instant.
5. Output hold: at the D/A side a hold keeps the actuator signal constant between updates (zero order hold), reconstructing a continuous signal.

Circuit

           Switch S (FET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
     Control (sample/hold) --> gate of S

• A1: input buffer with low output impedance for fast charging of C.
• S: MOSFET/JFET switch driven by the logic control signal.
• C: low-leakage hold capacitor.
• A2: output buffer with very high input impedance so C does not discharge.

Operation

Sample (tracking) mode: control signal closes S. C charges through A1 and $V_{out}$ follows $V_{in}$. The time to reach the input value within the required accuracy is the acquisition time.

Hold mode: at the sampling instant the control signal opens S. The charge on C is trapped because neither the open switch nor A2 draws current, so $V_{out}$ remains at $V_{in}(kT)$. The ADC converts this value.

 Vin     /‾‾\      /
        /    \____/
 Vout  /‾‾‾‾|____|‾‾|___
 Mode  track hold track hold

Performance terms

• Acquisition time: time to charge C to the input value in sample mode.
• Aperture time: delay between hold command and actual opening of S.
• Droop: slow decay during hold, $dV/dt = I_{leak}/C$.
• Feedthrough: input leaking to output during hold.
• Hold step (pedestal): small jump from charge injected by the switch.

Mathematically, the S/H is modelled as an ideal sampler followed by a zero order hold, $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$.

A sample-and-hold (S/H) circuit takes the value of an analog signal at a sampling instant and holds it constant for the time the A/D converter needs to convert it. It is placed between the multiplexer and the ADC in a data acquisition system.

           Switch S (FET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
     Control (sample/hold) --> gate of S

Components: input buffer A1 (low output impedance), electronic switch S (FET) driven by a logic control signal, hold capacitor C, and output buffer A2 (high input impedance).

Modes

• Sample/tracking mode: S closed; C charges and the output follows the input.
• Hold mode: S opened at the sampling instant; C keeps its charge and the output stays constant at $V_{in}(kT)$ while the ADC converts.

Why it is needed

• The ADC input must not change by more than half an LSB during conversion.
• One S/H and ADC can serve many multiplexed channels.
• Several S/H units allow simultaneous sampling of many signals.

Specifications

A large C reduces droop but increases acquisition time, so C is chosen as a compromise. In analysis, the S/H is modelled as an ideal sampler followed by a zero order hold with $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$.

A digital-to-analog converter (DAC) converts an n-bit binary word from the computer into a proportional analog voltage or current. In a digital control system it sits at the controller output, followed by a hold circuit and the actuator.

Output relation

$$V_o = V_{ref}\left(\frac{b_{n-1}}{2} + \frac{b_{n-2}}{4} + \cdots + \frac{b_0}{2^n}\right)$$

Resolution (one LSB) $= V_{ref}/2^n$.

Example: 4-bit DAC, $V_{ref} = 16$ V, input 1011: $V_o = 16(1/2 + 0 + 1/8 + 1/16) = 11$ V.

Common types

1. Weighted-resistor DAC: resistors $R, 2R, 4R, \dots, 2^{n-1}R$ feed an op-amp summer. Simple but needs a wide range of precise resistors.
2. R-2R ladder DAC: only two resistor values; each bit's current is halved at each node. Most widely used.

 Vref -+-2R-+-2R-+-2R-+
       |    |    |    |   R-2R ladder
      b3   b2   b1   b0 -> op-amp -> Vo

Specifications

• Resolution: number of bits or smallest output step.
• Accuracy and linearity: deviation from the ideal straight line.
• Settling time: time to reach final value within ±½ LSB.
• Monotonicity: output must not fall when the code increases.

The DAC output is held constant between updates by a latch/hold (zero order hold), giving a staircase signal.

A data hold circuit reconstructs a continuous signal from a sequence of samples by holding or extrapolating the last sample(s) until the next sample arrives. It is used after the D/A converter (and in S/H circuits) so the plant receives a continuous signal.

General form

Between $kT$ and $(k+1)T$ the output is a polynomial in $\tau$:

$$h(kT+\tau) = a_n\tau^n + \cdots + a_1\tau + x(kT), \quad 0 \le \tau < T$$

An $n$th-order hold uses the last $n+1$ samples.

Zero order hold (ZOH)

$h(kT+\tau) = x(kT)$; the output is a staircase.

$$G_{h0}(s) = \frac{1-e^{-Ts}}{s}$$

First order hold (FOH)

Straight-line extrapolation using the slope of the last two samples: $h(kT+\tau) = x(kT) + \frac{x(kT)-x((k-1)T)}{T}\tau$

$$G_{h1}(s) = \frac{Ts+1}{T}\left(\frac{1-e^{-Ts}}{s}\right)^2$$

 ZOH:  |‾‾|‾‾|‾‾      FOH:  / / /

Comparison

The ZOH is the standard hold in digital control because it is simple and its lag is small when $T$ is small.

Statement (sampling theorem): if $x(t)$ has no frequency components above $\omega_m$, it can be recovered completely from its samples only if the sampling frequency satisfies $\omega_s \ge 2\omega_m$ (strictly, $\omega_s > 2\omega_m$). The minimum rate $2\omega_m$ is the Nyquist rate.

Proof

The ideal sampler output is

$$x^*(t) = x(t)\sum_{k=-\infty}^{\infty}\delta(t-kT)$$

The impulse train is periodic with period $T$, so expand it as a Fourier series ($\omega_s = 2\pi/T$):

$$\sum_{k}\delta(t-kT) = \frac{1}{T}\sum_{n=-\infty}^{\infty} e^{jn\omega_s t}$$

Then

$$x^*(t) = \frac{1}{T}\sum_{n=-\infty}^{\infty} x(t)\,e^{jn\omega_s t}$$

Using the frequency-shift property $\mathcal{F}[x(t)e^{jn\omega_s t}] = X(j(\omega - n\omega_s))$:

$$X^*(j\omega) = \frac{1}{T}\sum_{n=-\infty}^{\infty} X(j(\omega + n\omega_s))$$

So the spectrum of the sampled signal is the original spectrum (scaled by $1/T$) repeated at every multiple of $\omega_s$.

Condition for no overlap

 ws > 2wm: no overlap
   /\        /\        /\
 -/--\------/--\------/--\--> w
 -ws   -wm  0  wm   ws
          |<-LPF->|

 ws < 2wm: overlap (aliasing)
   /\  /\  /\
 -/--\/--\/--\--> w

The primary band occupies $-\omega_m$ to $\omega_m$. The first copy occupies $\omega_s-\omega_m$ to $\omega_s+\omega_m$. They do not overlap if

$$\omega_s - \omega_m \ge \omega_m \quad\Rightarrow\quad \omega_s \ge 2\omega_m$$

Under this condition, an ideal low-pass filter with gain $T$ and cut-off $\omega_s/2$ removes all copies and returns $X(j\omega)$, i.e. $x(t)$ is recovered exactly. If $\omega_s < 2\omega_m$, the bands overlap (aliasing): high-frequency components appear as low frequencies, and no filter can separate them.

Hence the minimum sampling rate is $\omega_s = 2\omega_m$.

Example: a signal limited to 50 Hz must be sampled at more than 100 Hz. In practice control systems sample much faster (often 10 times the closed-loop bandwidth).

A data hold circuit converts a sequence of samples into a continuous signal by holding or extrapolating the sample value(s) between sampling instants. The simplest is the zero order hold (ZOH), which keeps each sample constant for one period: $h(kT+\tau) = x(kT)$, $0 \le \tau < T$, giving a staircase output.

Derivation of ZOH transfer function

Apply a unit impulse at $t=0$. The ZOH holds the value 1 for one sampling period and then drops to zero, so its impulse response is a rectangular pulse:

$$g_{h0}(t) = u(t) - u(t-T)$$

 g(t)
  1 |------+
    |      |
  0 +------+-------> t
    0      T

Taking the Laplace transform and using the shift theorem $\mathcal{L}[u(t-T)] = e^{-Ts}/s$:

$$\begin{aligned} G_{h0}(s) &= \frac{1}{s} - \frac{e^{-Ts}}{s} \\ &= \frac{1-e^{-Ts}}{s} \end{aligned}$$

This is the transfer function of the zero order hold.

Zero order hold and first order hold

A hold circuit reconstructs a continuous signal from samples by extrapolating between sampling instants with a polynomial of order $n$.

• Zero order hold (ZOH): holds the latest sample constant until the next one: $h(kT+\tau) = x(kT)$, $0 \le \tau < T$. Output is a staircase. It needs only the present sample.
• First order hold (FOH): extrapolates a straight line using the slope of the last two samples: $h(kT+\tau) = x(kT) + \dfrac{x(kT)-x((k-1)T)}{T}\,\tau$. Transfer function $G_{h1}(s) = \frac{Ts+1}{T}\left(\frac{1-e^{-Ts}}{s}\right)^2$.

 samples:  .   .   .   .
 ZOH:     |‾‾‾|‾‾‾|‾‾‾|‾‾‾
 FOH:      /   /   /   /

Transfer function of ZOH

Apply a unit impulse at $t=0$. The ZOH holds the value 1 for one sampling period and then drops to zero, so its impulse response is a rectangular pulse:

$$g_{h0}(t) = u(t) - u(t-T)$$

 g(t)
  1 |------+
    |      |
  0 +------+-------> t
    0      T

Taking the Laplace transform and using the shift theorem $\mathcal{L}[u(t-T)] = e^{-Ts}/s$:

$$\begin{aligned} G_{h0}(s) &= \frac{1}{s} - \frac{e^{-Ts}}{s} \\ &= \frac{1-e^{-Ts}}{s} \end{aligned}$$

Frequency response

With $s = j\omega$:

$$G_{h0}(j\omega) = T\,\frac{\sin(\omega T/2)}{\omega T/2}\,e^{-j\omega T/2}$$

so the ZOH acts as a low-pass filter with gain $T$ at low frequency, zero gain at multiples of $\omega_s$, and a phase lag of $\omega T/2$ (half-period delay).

Transfer function of ZOH

A zero order hold keeps each sample constant for one sampling period: $h(kT+\tau) = x(kT)$, $0 \le \tau < T$.

Apply a unit impulse at $t=0$. The ZOH holds the value 1 for one sampling period and then drops to zero, so its impulse response is a rectangular pulse:

$$g_{h0}(t) = u(t) - u(t-T)$$

 g(t)
  1 |------+
    |      |
  0 +------+-------> t
    0      T

Taking the Laplace transform and using the shift theorem $\mathcal{L}[u(t-T)] = e^{-Ts}/s$:

$$\begin{aligned} G_{h0}(s) &= \frac{1}{s} - \frac{e^{-Ts}}{s} \\ &= \frac{1-e^{-Ts}}{s} \end{aligned}$$

It can also be found from a general sampled input $x^*(t) = \sum x(kT)\delta(t-kT)$. The output is

$$h(t) = \sum_{k=0}^{\infty} x(kT)\,[u(t-kT) - u(t-(k+1)T)]$$ $$\begin{aligned} H(s) &= \sum_{k=0}^{\infty} x(kT)\,\frac{e^{-kTs} - e^{-(k+1)Ts}}{s} \\ &= \frac{1-e^{-Ts}}{s}\sum_{k=0}^{\infty} x(kT)e^{-kTs} = \frac{1-e^{-Ts}}{s}\,X^*(s) \end{aligned}$$

so $H(s)/X^*(s) = \frac{1-e^{-Ts}}{s}$.

Pulse transfer function

Since $e^{-Ts} = z^{-1}$:

$$\begin{aligned} G_{h0}(z) &= \mathcal{Z}\left[\frac{1-e^{-Ts}}{s}\right] = (1-z^{-1})\,\mathcal{Z}\left[\frac{1}{s}\right] \\ &= \frac{z-1}{z}\cdot\frac{z}{z-1} = 1 \end{aligned}$$

So the ZOH alone passes sample values unchanged ($h(kT) = x(kT)$). Its effect appears when it is followed by a plant $G_p(s)$:

$$G(z) = \mathcal{Z}\left[\frac{1-e^{-Ts}}{s}G_p(s)\right] = (1-z^{-1})\,\mathcal{Z}\left[\frac{G_p(s)}{s}\right]$$

Example: $G_p(s) = \frac{1}{s+1}$, $T = 1$ s.

$$\begin{aligned} \mathcal{Z}\left[\frac{1}{s(s+1)}\right] &= \frac{z(1-e^{-T})}{(z-1)(z-e^{-T})} \\ G(z) &= \frac{z-1}{z}\cdot\frac{z(1-e^{-T})}{(z-1)(z-e^{-T})} = \frac{1-e^{-T}}{z-e^{-T}} \\ &= \frac{0.6321}{z-0.3679} \end{aligned}$$

Answer: $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$; pulse transfer function of ZOH alone $=1$; ZOH with plant: $(1-z^{-1})\mathcal{Z}[G_p(s)/s]$.