- Asked 2/22
- 2077 Chaitra · 12 marks
Digital PI design, plant e^(−5s)/(s+0.4), Kv
Short answer
Sampling period T=2.5 s. PI controller GD(z)=0.2028(z-0.5873)/(z-1). Static velocity error constant Kv=0.0837 s^-1.
Consider a digital control system shown below. By choosing a reasonable sampling period T, design a digital PI controller such that the dominant closed loop poles have a damping ratio ζ of 0.5 and the number of samples per cycle of damped sinusoidal oscillation is 10. Also find the static velocity error constant. [Figure: unity-feedback loop: R(z) → summing junction → sampler (T) → digital PI controller → (1-e⁻ᵀˢ)/s → e⁻⁵ˢ/(s+0.4) → C(z)]
Step 1: Choice of sampling period
The plant has time constant s and dead time 5 s. Choose s:
- The dead time is then exactly , giving a clean .
- , which gives simple numbers.
- With 10 samples per cycle, the oscillation period is 25 s. This is reasonable for a process with 5 s dead time.
A smaller such as 1 s is not suitable. The dead time becomes , the phase lag at the desired point exceeds what a single PI zero can make up, and the angle condition cannot be met.
Step 2: Desired poles (ζ = 0.5, 10 samples per cycle)
Step 3: PI controller
Angles at :
- double pole at origin:
- pole at 0.3679:
- pole at 1:
The sum is , so the PI zero must add :
Step 4: Gain
so and .
Step 5: Static velocity error constant
The steady-state error for a unit ramp is .
Check: the closed-loop roots are (as designed), and . The extra real pole at 0.7562 is not cancelled by the PI zero (0.5873), so it adds a slow tail to the response.
Answer (with s): and .
✓ Answer checked by Claude Opus 5.5 (high effort)
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