TSI in random read, sequential write mode

A time switch or Time Slot Interchanger (TSI) moves the speech sample (PCM byte) in one time slot of an incoming TDM frame into a different time slot of the outgoing frame. In sequential write, random read mode (also called output-associated control), samples are written into memory in order and read out in the order set by a control memory.

Main parts

• Speech (data) memory, SM: $c$ locations, one per time slot, each 8 bits wide (one PCM sample). For a 32-channel PCM frame, $c = 32$.
• Control (connection) memory, CM: $c$ locations, each holding an SM address ($\log_2 c$ bits, 5 bits for 32 slots).
• Time-slot counter: a modulo-$c$ counter driven by the channel clock. It gives the current slot number $0, 1, \dots, c-1$.
• Write/read control logic and the processor interface that loads the CM when a call is set up.

 Input TDM                              Output TDM
 frame                                  frame
 ----->+---------------------+--------->
       |   Speech memory     |
       |   (c x 8 bits)      |
       +---------------------+
   write addr ^          ^ read addr
 (sequential) |          | (random)
       +-------------+  +------------+
       | Time-slot   |->| Control    |
       | counter     |  | memory     |
       +-------------+  +------------+
                             ^
                     processor (call set-up)

Working principle

1. Write phase (sequential): in time slot $i$ of the incoming frame, the sample is written into SM location $i$. The write address comes straight from the time-slot counter, so SM fills in order 0, 1, 2, ... every frame.
2. Read phase (random): in output time slot $j$, the counter addresses CM location $j$. CM($j$) contains the SM address of the input slot that must go out in slot $j$. That SM location is read and placed in output slot $j$.
3. When a call is set up, the processor writes the input slot number into the CM location of the wanted output slot. When the call is released, the entry is cleared.
4. Each slot needs one write and one read, so in every slot time the memory is accessed twice.

Example

Connect input TS3 to output TS7 (32-slot frame):

• In TS3 the sample is written into SM(3).
• The processor has stored CM(7) = 3.
• In TS7 the logic reads CM(7) = 3, then reads SM(3) and sends it in output slot 7.
• The sample is delayed by $7 - 3 = 4$ slots. If the output slot comes before the input slot, the sample goes out in the next frame (delay up to one frame, 125 µs).

Timing limit

Frame time is 125 µs, so slot time is $125/c$ µs. Since there are two accesses per slot, the memory cycle time must satisfy

$$t_{access} \le \frac{125\ \mu s}{2c}$$

For $c = 32$: $t_{access} \le 1.95$ µs. Faster memory allows more channels per TSI.

Features

• Strictly non-blocking: any input slot can go to any free output slot.
• Gives a fixed delay of less than one frame per stage.
• Size is limited by memory speed, so large exchanges combine T stages with S stages (TST).
• Broadcasting is easy: several CM locations can hold the same SM address, so one input can feed several outputs.