Compare TSI write/read modes

A TSI has a speech memory (SM) holding one PCM sample per time slot and a control memory (CM) set by the processor. The two modes differ in which access (write or read) the CM controls.

Sequential write, random read (output-associated control)

• Input sample in slot $i$ is written into SM($i$), using the time-slot counter as address.
• In output slot $j$, CM($j$) gives the SM address to read; the sample of that input slot is sent out.
• To connect input $i$ to output $j$: set CM($j$) = $i$.

Random write, sequential read (input-associated control)

• In input slot $i$, CM($i$) gives the SM address $j$ where the sample is written.
• SM is read in order, so SM($j$) goes out in output slot $j$.
• To connect input $i$ to output $j$: set CM($i$) = $j$.

 SW-RR:  in --> SM[counter]      SM[CM[counter]] --> out
 RW-SR:  in --> SM[CM[counter]]  SM[counter]     --> out

Example: input TS4 to output TS10. SW-RR: sample stored in SM(4), CM(10) = 4. RW-SR: CM(4) = 10, sample stored in SM(10). Output is the same in both.

Both modes need the same memory size ($c \times 8$ bits SM, $c \times \log_2 c$ bits CM) and are non-blocking for one frame. They are often used together in a TST switch (SW-RR at the input stage, RW-SR at the output stage), because then the control memories of all three stages are addressed by the same internal slot number $x$.