TSI in sequential read, random write mode

A time switch or TSI (Time Slot Interchanger) changes the time slot of a PCM sample within a TDM frame. In the sequential read, random write mode (also called input-associated control), the address at which each incoming sample is written is chosen by a control memory, and the speech memory is read out in order.

Main parts

• Speech memory (SM): $c$ words of 8 bits, one per time slot.
• Control memory (CM): $c$ words of $\log_2 c$ bits. CM($i$) holds the SM address where the sample of input slot $i$ must be written.
• Time-slot counter: a modulo-$c$ counter giving the current slot number.
• Processor interface: loads CM entries when calls are set up or released.

 Input TDM                              Output TDM
 --------->+---------------------+---------->
           |   Speech memory     |
           |   (c x 8 bits)      |
           +---------------------+
  write addr ^             ^ read addr
   (random)  |             | (sequential)
      +------------+  +-------------+
      | Control    |<-| Time-slot   |
      | memory     |  | counter     |
      +------------+  +-------------+
           ^
   processor (call set-up)

Working principle

1. Write phase (random): in input slot $i$, the counter addresses CM($i$). The value stored there, say $j$, is used as the write address, so the sample is stored in SM($j$).
2. Read phase (sequential): the counter also gives the read address directly. In output slot $j$, SM($j$) is read and sent out. So a sample written into SM($j$) leaves in output slot $j$.
3. To set up a call from input slot $i$ to output slot $j$, the processor writes $j$ into CM($i$).
4. One write and one read happen in every slot.

Example

Connect input TS2 to output TS9 in a 32-slot frame:

• Processor sets CM(2) = 9.
• In TS2 the sample is written into SM(9).
• In TS9 the counter reads SM(9), so the sample appears in output slot 9.
• Delay = $9 - 2 = 7$ slots $= 7 \times 3.9 \approx 27.3$ µs.

Timing

Slot time = $125/c$ µs and two memory accesses per slot are needed:

$$t_{access} \le \frac{125\ \mu s}{2c}$$

For 32 channels this is 1.95 µs. Maximum channels for a memory of access time $t$: $c_{max} = 125\ \mu s / 2t$.

Features

• Strictly non-blocking for its own frame.
• Delay is less than one frame (125 µs).
• Broadcast is not possible in this mode, because one input sample is written into only one SM location. (In sequential-write, random-read mode, several outputs can read the same location.)
• Commonly used for the output time stage of a TST switch: there the TSI's input slot is the internal slot $x$, so its control memory is addressed by the same slot number as the space-stage control memory.