Half subtractor using HDL

A half subtractor subtracts one bit B from another bit A and gives a Difference (D) and a Borrow (Bo).

$$D = A \oplus B, \qquad B_o = \bar A B$$

 A --+--[XOR]------------ D
 B --+--|
 A --[NOT]--[AND]-------- Bo
 B ---------|

Verilog HDL description

// Half subtractor: gate-level (structural) model
module half_sub_gate (input A, B, output D, Bo);
  wire An;              // complement of A
  xor g1 (D, A, B);     // D  = A XOR B
  not g2 (An, A);       // An = A'
  and g3 (Bo, An, B);   // Bo = A'B
endmodule

// Same circuit: dataflow model
module half_sub_df (input A, B, output D, Bo);
  assign D  = A ^ B;    // difference
  assign Bo = ~A & B;   // borrow
endmodule

Test bench (simulation)

module tb;
  reg A, B; wire D, Bo;
  half_sub_df uut (A, B, D, Bo);
  initial begin
    $monitor("A=%b B=%b D=%b Bo=%b", A, B, D, Bo);
    {A,B} = 2'b00; #10 {A,B} = 2'b01;
    #10 {A,B} = 2'b10; #10 {A,B} = 2'b11;
    #10 $finish;
  end
endmodule

Simulation output matches the truth table, e.g. A=0 B=1 D=1 Bo=1 and A=1 B=1 D=0 Bo=0.