HDL and 2-to-4 decoder in HDL

HDL

A Hardware Description Language (HDL) is a computer language used to describe the structure and behaviour of digital circuits in text form. The description can be simulated to check the design and synthesised into gates for an FPGA, CPLD or ASIC. Common HDLs are Verilog and VHDL. A design can be written at gate level (structural), dataflow (assign equations) or behavioural (always blocks) level.

2-to-4 line decoder

Inputs A1 A0 and enable E; exactly one output goes HIGH for each input code when E = 1.

$D_0 = E\bar A_1 \bar A_0$, $D_1 = E\bar A_1 A_0$, $D_2 = E A_1 \bar A_0$, $D_3 = E A_1 A_0$

Verilog (dataflow model)

module decoder2to4 (input A1, A0, E,
                   output D0, D1, D2, D3);
  assign D0 = E & ~A1 & ~A0; // 00
  assign D1 = E & ~A1 &  A0; // 01
  assign D2 = E &  A1 & ~A0; // 10
  assign D3 = E &  A1 &  A0; // 11
endmodule

Verilog (gate-level model)

module decoder2to4_g (input A1, A0, E,
                     output D0, D1, D2, D3);
  wire n1, n0;
  not (n1, A1);           // A1'
  not (n0, A0);           // A0'
  and (D0, E, n1, n0);
  and (D1, E, n1, A0);
  and (D2, E, A1, n0);
  and (D3, E, A1, A0);
endmodule

With E = 1 and A1A0 = 10, simulation gives D3D2D1D0 = 0100.