K-map Π(0,1,4,7,8,10,11,12)+d, NAND

Given $F = \Pi M(0,1,4,7,8,10,11,12)$ with don't-cares $d(2,3,6,9,15)$. The maxterms are the 0-cells, so the 1-cells are 5, 13, 14.

K-map

        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | 0 | 0 | X | X |
      +---+---+---+---+
 01   | 0 | 1 | 0 | X |
      +---+---+---+---+
 11   | 0 | 1 | X | 1 |
      +---+---+---+---+
 10   | 0 | X | 0 | 0 |
      +---+---+---+---+

Grouping the 1s (don't-care 6 is used with 14):

• Pair m(5,13) → $B\overline{C}D$
• Pair m(6,14) → $BC\overline{D}$

$$F = B\overline{C}D + BC\overline{D} = B(C \oplus D)$$

Check: 5 and 13 by $B\overline{C}D$; 14 by $BC\overline{D}$. ($ABC$, cells 14 and 15, can replace the second term with the same cost.)

NAND-only implementation

An SOP expression maps directly to a two-level NAND-NAND circuit (De Morgan: $X + Y = \overline{\overline{X}\cdot\overline{Y}}$). Each product term becomes a first-level NAND and the output NAND replaces the OR gate. Complemented inputs are made with NAND gates whose inputs are tied.

$$F = \overline{\overline{B\overline{C}D}\cdot\overline{BC\overline{D}}}$$

C ──[NAND]── C'   (inputs tied)
D ──[NAND]── D'   (inputs tied)

B, C', D ──[NAND]── P1  ─┐
                         ├──[NAND]── F
B, C, D' ──[NAND]── P2  ─┘

Gates: 2 NAND inverters, two 3-input NANDs and one 2-input output NAND: 5 NAND gates.