K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND

Given $F(A,B,C,D) = \Sigma m(1,2,3,8,9,10,11,14) + d(0,4,12)$, where X marks a don't-care cell.

K-map simplification

        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | X | 1 | 1 | 1 |
      +---+---+---+---+
 01   | X | 0 | 0 | 0 |
      +---+---+---+---+
 11   | X | 0 | 0 | 1 |
      +---+---+---+---+
 10   | 1 | 1 | 1 | 1 |
      +---+---+---+---+

Groups (don't-cares 0 and 12 are used where they make a group bigger; don't-care 4 is left out):

• Octet m(0,1,2,3,8,9,10,11) → $\overline{B}$
• Quad m(8,10,12,14) → $A\overline{D}$

$$F = \overline{B} + A\overline{D}$$

Check: the octet covers 1, 2, 3, 8, 9, 10, 11, and the quad covers 8, 10, 14 (with 12). All minterms are covered.

Realization using NAND gates

Take double complement and apply De Morgan's theorem:

$$\begin{aligned} F &= \overline{\overline{\overline{B} + A\overline{D}}} \\ &= \overline{B \cdot \overline{A\overline{D}}} \end{aligned}$$

So $F$ = NAND($B$, NAND($A$, $\overline{D}$)). $\overline{D}$ is made with a NAND gate whose inputs are tied together. The single literal $\overline{B}$ goes into the output NAND as plain $B$.

D ──[NAND]── D'   (inputs tied)

A, D' ──[NAND]── P1  ─┐
                      ├──[NAND]── F
B     ──────────     ─┘

Total: 3 two-input NAND gates (one used as an inverter).