Octal priority encoder design

An octal (8-to-3) priority encoder has eight inputs $D_0$–$D_7$ and three outputs $Y_2Y_1Y_0$ giving the binary code of the highest-numbered active input ($D_7$ = highest priority). A valid output $V$ is 1 when any input is active. The 74148 is a common IC (active-low).

Truth table (X = don't care)

Output equations

Write each output as the OR of the rows where it is 1; each row requires all higher inputs to be 0, and redundant conditions are dropped.

• $Y_2 = 1$ for highest input 4, 5, 6 or 7:

$$Y_2 = D_4 + D_5 + D_6 + D_7$$

• $Y_1 = 1$ for highest input 2, 3, 6 or 7. Inputs 2 and 3 count only if $D_4 = D_5 = 0$ (if $D_6$ or $D_7$ is 1, $Y_1$ is 1 anyway):

$$Y_1 = D_7 + D_6 + D_5'D_4'D_3 + D_5'D_4'D_2$$

• $Y_0 = 1$ for highest input 1, 3, 5 or 7:

$$Y_0 = D_7 + D_6'D_5 + D_6'D_4'D_3 + D_6'D_4'D_2'D_1$$

• Valid bit:

$$V = D_0 + D_1 + \dots + D_7$$

Logic diagram

 D4,D5,D6,D7 ----------------------[OR 4]--- Y2

 D7 ---------------------------+
 D6 ---------------------------+
 D5',D4',D3 ---[AND 3]---------+--[OR 4]--- Y1
 D5',D4',D2 ---[AND 3]---------+

 D7 ---------------------------+
 D6',D5 -------[AND 2]---------+
 D6',D4',D3 ---[AND 3]---------+--[OR 4]--- Y0
 D6',D4',D2',D1 [AND 4]--------+

 D0 ... D7 ------------------------[OR 8]--- V

Inverters provide $D_2', D_4', D_5', D_6'$.

Operation

When several keys or interrupt lines are active together, only the highest one is encoded. Example: $D_6 = D_3 = D_1 = 1$, others 0. Then $Y_2 = 1$, $Y_1 = 1$ (from $D_6$), $Y_0 = 0$ (since $D_6' = 0$ blocks all $Y_0$ terms and $D_7 = 0$). Output $110 = 6$ and $V = 1$. All 255 non-zero input patterns were checked against these equations.