Effect of input bias currents and mitigation

Input bias currents IB1 and IB2 are the dc base currents drawn by the input transistors of the op-amp. They flow through the external resistors and create a dc output voltage even when the input signal is zero.

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

Take Vi = 0 (only bias currents act). IB1 flows into the inverting input and IB2 into the non-inverting input.

Without compensation (Rcomp = 0): the non-inverting input is at 0 V, so the inverting input is also at 0 V (virtual ground). No current flows in R1, so all of IB1 comes through Rf:

Vo = IB1 · Rf

e.g. IB = 500 nA, Rf = 1 MΩ gives 0.5 V of output error with no input.

With compensation resistor Rcomp at the non-inverting input:

V+ = -IB2·Rcomp = V-
KCL at inverting node:
  (0 - V-)/R1 + (Vo - V-)/Rf = IB1
  Vo = IB1·Rf + V-(1 + Rf/R1)
     = IB1·Rf - IB2·Rcomp(1 + Rf/R1)
Choose Rcomp(1 + Rf/R1) = Rf, i.e.
  Rcomp = R1·Rf/(R1 + Rf) = R1 ‖ Rf
Then
  Vo = Rf (IB1 - IB2) = Rf · Ios

Since Ios is only a fraction of IB (for the 741, 20 nA against 80 nA typical), the error falls a lot. The rule is: both inputs should see the same dc resistance to ground.

Other ways to reduce the effect of bias currents:

• Use op-amps with low IB (FET-input or super-β types, e.g. LF351, CA3140 with IB in pA).
• Keep Rf (and all resistors) low, since the error is IB·Rf or Ios·Rf.
• Use a T-network feedback to get high gain with smaller resistors.
• Use the offset-null terminals (pins 1 and 5 on the 741 with a 10 kΩ pot) or an external balancing network to trim the remaining output offset to zero.
• For ac amplifiers, use capacitor coupling so the dc gain is 1.