Bias and offset currents: effects and reduction

Input bias current and input offset current

• Input bias current (IB): the average of the dc currents flowing into the two inputs when the output is zero, IB = (IB1 + IB2)/2. It is the base current needed to bias the input transistors (741: 80 nA typical, 500 nA max).
• Input offset current (Ios): the difference between the two input currents, Ios = |IB1 − IB2|, caused by β mismatch (741: 20 nA typical, 200 nA max).

Effect of input bias currents on output voltage

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

With Vi = 0 and Rcomp = 0, the inverting input is at virtual ground, so no current flows in R1 and the whole of IB1 must come from the output through Rf:

Vo = IB1 · Rf

So the output has a dc error with no input. Example: IB1 = 500 nA, Rf = 1 MΩ gives Vo = 0.5 V. This error adds to the signal, shifts the operating point, and in integrators (Rf replaced by a capacitor) charges the capacitor until the output saturates.

Reducing the effect of input bias currents

Compensating resistor: connect Rcomp from the non-inverting input to ground:

V+ = V- = -IB2·Rcomp
Vo = IB1·Rf - IB2·Rcomp(1 + Rf/R1)
With Rcomp = R1 ‖ Rf = R1·Rf/(R1 + Rf):
Vo = Rf (IB1 - IB2) = Rf · Ios

Since Ios is much smaller than IB, the output error drops (in the example above, with Ios = 200 nA it falls from 0.5 V to 0.2 V).

Other ways to reduce the effect of bias currents:

• Use op-amps with low IB (FET-input or super-β types, e.g. LF351, CA3140 with IB in pA).
• Keep Rf (and all resistors) low, since the error is IB·Rf or Ios·Rf.
• Use a T-network feedback to get high gain with smaller resistors.
• Use the offset-null terminals (pins 1 and 5 on the 741 with a 10 kΩ pot) or an external balancing network to trim the remaining output offset to zero.
• For ac amplifiers, use capacitor coupling so the dc gain is 1.