Effect of input offset voltage; PSRR

Effect of input offset voltage

Input offset voltage (Vio) is the small dc voltage that must be applied between the inputs to make the output zero. It is caused by mismatch of the input transistors (VBE and β). Its effect can be modelled as a dc source Vio in series with the non-inverting input of an ideal op-amp.

            Rf
      +---/\/\/---+
      |            |
 GND -R1--+--(-)   |
          |     >--+---- Voo
 GND --[Vio]--(+)

With the signal input grounded, the circuit is a non-inverting amplifier for Vio:

Voo = (1 + Rf/R1) · Vio

So the offset is amplified by the noise gain (1 + Rf/R1), the same for inverting and non-inverting configurations. Example: Vio = 6 mV, R1 = 1 kΩ, Rf = 100 kΩ gives Voo = 101 × 6 mV = 0.606 V at the output with no input. In open loop (comparator) even 1 mV can drive the output into saturation.

Minimizing the offset

• Offset null terminals: for the 741, a 10 kΩ potentiometer between pins 1 and 5 with the wiper to −VEE is adjusted for zero output.
• External balancing (compensating) network: a small adjustable voltage from a potentiometer across ±V, divided down, applied to the free input.
• Use low-offset op-amps (e.g. OP07, Vio ≈ 25 µV) or chopper-stabilized op-amps.
• Reduce dc gain: use the lowest gain needed; in ac amplifiers use a capacitor in series with R1 so the dc gain is 1.
• Keep the op-amp at a stable temperature, since Vio drifts (µV/°C).

Power supply rejection ratio (PSRR)

PSRR (also called supply voltage rejection ratio, SVRR) is the change in input offset voltage per unit change in supply voltage, with the other supply constant:

PSRR = ΔVio / ΔV    (µV/V)
PSRR(dB) = 20 log10 (ΔV / ΔVio)

For the 741, PSRR = 30 µV/V typical (150 µV/V max). A smaller value in µV/V (or a larger value in dB) is better.