FDNR realization of 5th order ladder at 25,000 rad/s

FDNR

A frequency dependent negative resistor (FDNR) is a one-port with impedance $Z(s) = \dfrac{1}{s^2D}$. At $s = j\omega$, $Z = -\dfrac{1}{\omega^2 D}$: a real, negative resistance whose size falls as $1/\omega^2$. $D$ (unit F²Ω) is its constant. It cannot be made from passive elements; a GIC with two capacitors realises it.

Realisation

The FDNR is realised with a GIC (Antoniou circuit):

   Iin  node 1
 o-->-----+--------------(+) A1
 Vin      |
         [Z1]
          +--- node 2 ---- output of A1
         [Z2]
          +--- node 3 ---- (-) A1 and (-) A2
         [Z3]
          +--- node 4 ---- output of A2
         [Z4]
          +--- node 5 ---- (+) A2
         [Z5]
          |
         GND

Put capacitors in positions 1 and 5 ($Z_1 = 1/sC_1$, $Z_5 = 1/sC_5$) and resistors in 2, 3, 4:

$$Z_{in} = \frac{R_3}{s^2 C_1 C_5 R_2 R_4} = \frac{1}{s^2 D}, \qquad D = \frac{C_1 C_5 R_2 R_4}{R_3}$$

With $C_1 = C_5 = C$ and $R_2 = R_3 = R_4 = R$: $D = C^2 R$. At $s = j\omega$, $Z_{in} = -1/(\omega^2 D)$, a negative resistance whose value depends on frequency: an FDNR (also called a D-element or supercapacitor).

Design: 5th-order Butterworth LPF, $\omega_0$ = 25,000 rad/s

Given prototype: $R_s = 1\ \Omega$, $L_1 = 0.618$ H, $C_2 = 1.618$ F, $L_3 = 2$ H, $C_4 = 1.618$ F, $L_5 = 0.618$ H, $R_L = 1\ \Omega$.

Step 1: Bruton transformation (divide all impedances by $s$): source and load resistors (1 Ω) become 1 F capacitors, each inductor $L$ becomes a resistor of $L$ Ω, each shunt capacitor $C$ becomes a grounded FDNR with $D = C$.

Step 2: Scaling. Frequency scaling factor $\omega_0 = 25{,}000\ \text{rad/s}$. Choose the terminating capacitors as $C_t$ = 10 nF, so

$$k_z = \frac{1}{\omega_0 C_t} = \frac{1}{25000 \times 1 \times 10^{-8}} = 4000\ \Omega$$ $$\begin{aligned} R_{new} &= k_z R, \qquad C_{new} = \frac{C}{k_z\,\omega_0}, \qquad D_{new} = \frac{D}{k_z\,\omega_0^2} \end{aligned}$$

Step 3: Element values. Each FDNR is a GIC with $C_1 = C_5 = C$ and $R_2 = R_3 = R_4 = R_D$, so $D = C^2R_D$. Taking $C = C_t$ gives $R_D = D_{new}/C_t^2 = k_z D$.

Step 4: DC path. The source and load capacitors block DC, and the op-amps in the GICs need a DC bias path. Put $R_a$ across the source capacitor and $R_b$ across the load capacitor. They must be much larger than $k_z$ (the capacitor impedance at $\omega_0$). At DC the FDNRs are open, so the DC gain is $R_b/(R_a + \Sigma R + R_b)$. To keep the prototype DC gain of 1/2, set $R_b = R_a + \Sigma R$:

$R_a$ = 100 kΩ, $\Sigma R$ = 12.94 kΩ, so $R_b$ = 112.9 kΩ.

Final circuit ($C_s \| R_a$ in series from the source, $C_L \| R_b$ as the load, each $D_k$ a GIC FDNR to ground):

Vi o--[Cs||Ra]--[R1]-+----[R3]-+----[R5]-+----o Vo
                     |         |         |
                    [D2]      [D4]    [CL||Rb]
GND ----------------------------------------------

Answer: terminating capacitors 10 nF; series resistors 2.472 kΩ, 8 kΩ, 2.472 kΩ; two FDNRs, each a GIC with C = 10 nF and $R_D$ = 6.472 kΩ; $R_a$ = 100 kΩ, $R_b$ = 112.9 kΩ.