FDNR simulation of 4th order Butterworth LPF

The inductors of the resistively terminated LC ladder are removed with the Bruton transformation (divide every impedance by $s$), and the grounded capacitors become FDNRs ($Z = 1/s^2D$), each realised by a GIC.

From the table (n = 4), the doubly terminated Butterworth prototype (1 Ω terminations, $\omega_0 = 1$ rad/s) is $R_s = 1$, $L_1 = 0.7654$ H, $C_2 = 1.848$ F, $L_3 = 1.848$ H, $C_4 = 0.7654$ F, $R_L = 1\ \Omega$ (series L first, shunt C to ground).

Normalised FDNR network ($\omega_0 = 1$ rad/s): source capacitor 1 F, $R_1 = 0.7654\ \Omega$, FDNR $D_2 = 1.848$, $R_3 = 1.848\ \Omega$, FDNR $D_4 = 0.7654$, load capacitor 1 F.

No frequency is given, so the design is shown denormalised to a practical example of $\omega_0$ = 10,000 rad/s:

FDNR from a GIC. Each FDNR is made with an Antoniou GIC (two op-amps, five impedances $Z_1$ to $Z_5$ in a chain with $Z_5$ grounded, so that $Z_{in} = Z_1Z_3Z_5/(Z_2Z_4)$). Put capacitors in positions 1 and 5 ($Z_1 = 1/sC_1$, $Z_5 = 1/sC_5$) and resistors in 2, 3, 4:

$$Z_{in} = \frac{R_3}{s^2 C_1 C_5 R_2 R_4} = \frac{1}{s^2 D}, \qquad D = \frac{C_1 C_5 R_2 R_4}{R_3}$$

With $C_1 = C_5 = C$ and $R_2 = R_3 = R_4 = R$: $D = C^2 R$. At $s = j\omega$, $Z_{in} = -1/(\omega^2 D)$, a negative resistance whose value depends on frequency: an FDNR (also called a D-element or supercapacitor).

Step 1: Bruton transformation (divide all impedances by $s$): source and load resistors (1 Ω) become 1 F capacitors, each inductor $L$ becomes a resistor of $L$ Ω, each shunt capacitor $C$ becomes a grounded FDNR with $D = C$.

Step 2: Scaling. Frequency scaling factor $\omega_0 = 10^4\ \text{rad/s}$. Choose the terminating capacitors as $C_t$ = 10 nF, so

$$k_z = \frac{1}{\omega_0 C_t} = \frac{1}{10000 \times 1 \times 10^{-8}} = 10000\ \Omega$$ $$\begin{aligned} R_{new} &= k_z R, \qquad C_{new} = \frac{C}{k_z\,\omega_0}, \qquad D_{new} = \frac{D}{k_z\,\omega_0^2} \end{aligned}$$

Step 3: Element values. Each FDNR is a GIC with $C_1 = C_5 = C$ and $R_2 = R_3 = R_4 = R_D$, so $D = C^2R_D$. Taking $C = C_t$ gives $R_D = D_{new}/C_t^2 = k_z D$.

Step 4: DC path. The source and load capacitors block DC, and the op-amps in the GICs need a DC bias path. Put $R_a$ across the source capacitor and $R_b$ across the load capacitor. They must be much larger than $k_z$ (the capacitor impedance at $\omega_0$). At DC the FDNRs are open, so the DC gain is $R_b/(R_a + \Sigma R + R_b)$. To keep the prototype DC gain of 1/2, set $R_b = R_a + \Sigma R$:

$R_a$ = 1 MΩ, $\Sigma R$ = 26.13 kΩ, so $R_b$ = 1.026 MΩ.

Final circuit ($C_s \| R_a$ in series from the source, $C_L \| R_b$ as the load, each $D_k$ a GIC FDNR to ground):

Vi o--[Cs||Ra]--[R1]-+----[R3]-+-------+----o Vo
                     |         |       |
                    [D2]      [D4]  [CL||Rb]
GND --------------------------------------------

Answer (for $\omega_0$ = 10⁴ rad/s): terminating capacitors 10 nF; series resistors 7.654 kΩ and 18.48 kΩ; FDNR GICs with C = 10 nF and $R_D$ = 18.48 kΩ ($D_2$) and 7.654 kΩ ($D_4$); $R_a$ = 1 MΩ, $R_b$ = 1.026 MΩ. For any other $\omega_0$, use $k_z = 1/(\omega_0 C_t)$ and the same steps.