FDNR LPF at 4.5 kHz with 0.1 μF

FDNR and how it avoids inductors

A frequency dependent negative resistor (FDNR) is a one-port with impedance $Z(s) = \dfrac{1}{s^2D}$. At $s = j\omega$, $Z = -\dfrac{1}{\omega^2 D}$: a real, negative resistance whose size falls as $1/\omega^2$. $D$ (unit F²Ω) is its constant. It cannot be made from passive elements; a GIC with two capacitors realises it.

Under the Bruton transformation (all impedances divided by $s$) a resistor becomes a capacitor, an inductor becomes a resistor and a capacitor becomes an FDNR. A lowpass ladder therefore turns into a network of R, C and grounded FDNRs with the same transfer function, and each FDNR is one Antoniou GIC (two op-amps, five impedances $Z_1$ to $Z_5$ in a chain with $Z_5$ grounded, so that $Z_{in} = Z_1Z_3Z_5/(Z_2Z_4)$) with capacitors in positions 1 and 5 and resistors in positions 2, 3, 4, so $D = C^2R$. No inductor remains.

Design: 4.5 kHz, largest capacitor 0.1 μF

Given prototype (4th-order Butterworth, 1 rad/s): series $L_1 = 0.7654$ H, shunt $C_2 = 1.848$ F, series $L_3 = 1.848$ H, shunt $C_4 = 0.7654$ F, 1 Ω terminations.

Step 1: Bruton transformation (divide all impedances by $s$): source and load resistors (1 Ω) become 1 F capacitors, each inductor $L$ becomes a resistor of $L$ Ω, each shunt capacitor $C$ becomes a grounded FDNR with $D = C$.

Step 2: Scaling. Frequency scaling factor $\omega_0 = 2\pi(4500) = 28{,}274\ \text{rad/s}$. Choose the terminating capacitors as $C_t$ = 100 nF (the largest capacitor allowed; all capacitors are made 0.1 μF), so

$$k_z = \frac{1}{\omega_0 C_t} = \frac{1}{28274.3 \times 1 \times 10^{-7}} = 353.68\ \Omega$$ $$\begin{aligned} R_{new} &= k_z R, \qquad C_{new} = \frac{C}{k_z\,\omega_0}, \qquad D_{new} = \frac{D}{k_z\,\omega_0^2} \end{aligned}$$

Step 3: Element values. Each FDNR is a GIC with $C_1 = C_5 = C$ and $R_2 = R_3 = R_4 = R_D$, so $D = C^2R_D$. Taking $C = C_t$ gives $R_D = D_{new}/C_t^2 = k_z D$.

Step 4: DC path. The source and load capacitors block DC, and the op-amps in the GICs need a DC bias path. Put $R_a$ across the source capacitor and $R_b$ across the load capacitor. They must be much larger than $k_z$ (the capacitor impedance at $\omega_0$). At DC the FDNRs are open, so the DC gain is $R_b/(R_a + \Sigma R + R_b)$. To keep the prototype DC gain of 1/2, set $R_b = R_a + \Sigma R$:

$R_a$ = 10 kΩ, $\Sigma R$ = 924.3 Ω, so $R_b$ = 10.92 kΩ.

Final circuit ($C_s \| R_a$ in series from the source, $C_L \| R_b$ as the load, each $D_k$ a GIC FDNR to ground):

Vi o--[Cs||Ra]--[R1]-+----[R3]-+-------+----o Vo
                     |         |       |
                    [D2]      [D4]  [CL||Rb]
GND --------------------------------------------

Answer: all capacitors 0.1 μF; series resistors 270.7 Ω and 653.6 Ω; FDNR GICs with C = 0.1 μF and $R_D$ = 653.6 Ω ($D_2$) and 270.7 Ω ($D_4$); $R_a$ = 10 kΩ, $R_b$ = 10.92 kΩ.