- 2080 Bhadra · 2+4 marks
FDNR RLC equivalent; 4th order LPF at 1 kHz
Short answer
FDNR, impedance 1/(s²D), avoids inductors. A series R-L-C branch is transformed to C-R-FDNR. For 1 kHz, C_t=0.01 μF, ω0=6283 rad/s, k_z=15.9 kΩ. Terminations become 10 nF; series L become 29.4 kΩ and 12.2 kΩ; FDNR GICs use C=10 nF, R_D=12.2 kΩ, 29.4 kΩ; DC bias R_a=1 MΩ, R_b=1.04 MΩ.
Draw the figure of RLC series circuit using FDNR. Use fourth order Butterworth low pass by FDNR with half power = 1×10³ Hz and capacitor in final design = 0.01μF. [Figure: source V1, 1 Ω source resistor, shunt 0.7654 F, series 1.848 H, shunt 1.848 F, series 0.7654 H, 1 Ω load]
RLC elements using FDNR (Bruton transformation)
Dividing every impedance by keeps the voltage transfer function the same and changes each element as follows:
Element Impedance /s New element
--[ R ]-- R R/s --| C=1/R |--
--(LLL)-- sL L --[ R=L ]--
--| C |-- 1/sC 1/(s^2 C) --[FDNR D=C]--
So a series R–L–C branch becomes a series C–R–FDNR branch:
Before: o--[ R ]--(LLL)--| C |--o
After: o--| 1/R |--[ L ]--[D = C]--o
In a lowpass ladder the capacitors are grounded, so the FDNRs are grounded and each is one Antoniou GIC (two op-amps, five impedances to in a chain with grounded, so that ) with capacitors in positions 1 and 5 and resistors in positions 2, 3, 4, so .
Design: 4th-order Butterworth LPF, 1 kHz, capacitors 0.01 μF
Given ladder (1 rad/s, 1 Ω): shunt F, series H, shunt F, series H, load 1 Ω.
Step 1: Bruton transformation (divide all impedances by ): source and load resistors (1 Ω) become 1 F capacitors, each inductor becomes a resistor of Ω, each shunt capacitor becomes a grounded FDNR with .
Step 2: Scaling. Frequency scaling factor . Choose the terminating capacitors as = 10 nF (all capacitors in the final design), so
Step 3: Element values. Each FDNR is a GIC with and , so . Taking gives .
| Prototype | After Bruton | Scaled | Final element |
|---|---|---|---|
| F | 10 nF | ||
| F (shunt) | FDNR | GIC: C = 10 nF, = 12.18 kΩ | |
| H (series) | 29.41 kΩ | ||
| F (shunt) | FDNR | GIC: C = 10 nF, = 29.41 kΩ | |
| H (series) | 12.18 kΩ | ||
| F | 10 nF |
Step 4: DC path. The source and load capacitors block DC, and the op-amps in the GICs need a DC bias path. Put across the source capacitor and across the load capacitor. They must be much larger than (the capacitor impedance at ). At DC the FDNRs are open, so the DC gain is . To keep the prototype DC gain of 1/2, set :
= 1 MΩ, = 41.59 kΩ, so = 1.042 MΩ.
Final circuit ( in series from the source, as the load, each a GIC FDNR to ground):
Vi o--[Cs||Ra]-+----[R2]-+----[R4]-+----o Vo
| | |
[D1] [D3] [CL||Rb]
GND ----------------------------------------
Answer: all capacitors 0.01 μF; series resistors 29.41 kΩ and 12.18 kΩ; FDNR GICs with C = 0.01 μF and = 12.18 kΩ () and 29.41 kΩ (); = 1 MΩ, = 1.042 MΩ.
✓ Answer checked by Claude Sonnet 5.5
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