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Short note: Sample and hold circuit

Short answer

A sample-and-hold circuit captures an analog signal value at the sampling instant and holds it constant during ADC conversion. It consists of an input buffer, FET switch, hold capacitor, and output buffer. In sample mode the output tracks the input; in hold mode the switch opens and the capacitor maintains the voltage. It prevents ADC errors, enables multiplexing, and allows simultaneous sampling. Key specifications are acquisition time, aperture time, droop, and feedthrough.

Write a short note on sample and hold circuit.

A sample-and-hold (S/H) circuit takes the value of an analog signal at a sampling instant and holds it constant for the time the A/D converter needs to convert it. It is placed between the multiplexer and the ADC in a data acquisition system.

           Switch S (FET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
     Control (sample/hold) --> gate of S

Components: input buffer A1 (low output impedance), electronic switch S (FET) driven by a logic control signal, hold capacitor C, and output buffer A2 (high input impedance).

Modes

  • Sample/tracking mode: S closed; C charges and the output follows the input.
  • Hold mode: S opened at the sampling instant; C keeps its charge and the output stays constant at Vin(kT)V_{in}(kT) while the ADC converts.

Why it is needed

  • The ADC input must not change by more than half an LSB during conversion.
  • One S/H and ADC can serve many multiplexed channels.
  • Several S/H units allow simultaneous sampling of many signals.

Specifications

TermMeaning
Acquisition timeTime for output to settle to input in sample mode
Aperture timeDelay between hold command and switch opening
Droop rateIleak/CI_{leak}/C, fall of voltage during hold
FeedthroughInput appearing at output during hold

A large C reduces droop but increases acquisition time, so C is chosen as a compromise. In analysis, the S/H is modelled as an ideal sampler followed by a zero order hold with Gh0(s)=1−e−TssG_{h0}(s) = \frac{1-e^{-Ts}}{s}.

✓ Answer checked by Claude Opus 5.5 (high effort)

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