Importance and operation of sample and hold

A sample-and-hold (S/H) circuit samples an analog signal at an instant and holds that value constant for a given time.

Why S/H is important

1. Steady input for the A/D converter: an ADC (e.g. successive approximation) needs several microseconds to convert. If the input changes during this time by more than half an LSB, the output code is wrong. The S/H freezes the input during conversion.
2. Allows fast signals to be converted: without S/H, a 12-bit ADC with 10 µs conversion time can only handle signals of a few hertz; with S/H, much higher frequencies.
3. Multiplexing: in a multichannel system one S/H and ADC serve many channels; the S/H keeps each sample while the multiplexer moves on.
4. Simultaneous sampling: several S/H circuits can capture many signals at the same instant.
5. Output hold: at the D/A side a hold keeps the actuator signal constant between updates (zero order hold), reconstructing a continuous signal.

Circuit

           Switch S (FET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
     Control (sample/hold) --> gate of S

• A1: input buffer with low output impedance for fast charging of C.
• S: MOSFET/JFET switch driven by the logic control signal.
• C: low-leakage hold capacitor.
• A2: output buffer with very high input impedance so C does not discharge.

Operation

Sample (tracking) mode: control signal closes S. C charges through A1 and $V_{out}$ follows $V_{in}$. The time to reach the input value within the required accuracy is the acquisition time.

Hold mode: at the sampling instant the control signal opens S. The charge on C is trapped because neither the open switch nor A2 draws current, so $V_{out}$ remains at $V_{in}(kT)$. The ADC converts this value.

 Vin     /‾‾\      /
        /    \____/
 Vout  /‾‾‾‾|____|‾‾|___
 Mode  track hold track hold

Performance terms

• Acquisition time: time to charge C to the input value in sample mode.
• Aperture time: delay between hold command and actual opening of S.
• Droop: slow decay during hold, $dV/dt = I_{leak}/C$.
• Feedthrough: input leaking to output during hold.
• Hold step (pedestal): small jump from charge injected by the switch.

Mathematically, the S/H is modelled as an ideal sampler followed by a zero order hold, $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$.