Setup/hold time; SR to JK conversion

Setup time and hold time

• Setup time ($t_{su}$): the minimum time the data input (D, J, K, S, R) must be stable before the active clock edge so that the flip-flop reads it correctly.
• Hold time ($t_h$): the minimum time the data input must stay stable after the active clock edge.

Data   ===X======STABLE=======X====
             |<-tsu->|<-th->|
CLK    ______________|‾‾‾‾‾‾‾‾‾‾‾‾
                     ^ active edge

If either is violated the flip-flop may store a wrong value or go metastable. Both are given in the data sheet; for LS-TTL flip-flops they are of the order of tens of ns ($t_{su}$) and a few ns ($t_h$).

SR flip-flop into JK flip-flop

We add a combinational circuit with inputs J, K and $Q_n$ that drives S and R.

SR excitation table

Conversion table

K-maps

 S:      KQn=00 01 11 10    R:     KQn=00 01 11 10
  J=0       0   X  0  0      J=0      X   0  1  X
  J=1       1   X  0  1      J=1      0   0  1  0

$$S = J\,Q_n', \qquad R = K\,Q_n$$

Circuit

J --[AND]-- S +--------+--+-- Q
Q'--[   ]     | SR FF  |  |
              |  CLK   |  |
K --[AND]-- R |        |--|-+-- Q'
Q --[   ]     +--------+  | |
   (feedback of Q, Q' to the AND gates)

Check: $J = K = 1$, $Q_n = 1$: $S = 0$, $R = 1$, so Q resets (toggle). The two AND gates never make $S = R = 1$, so the invalid state is removed.