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Two-level bus architecture

Short answer

A two-level bu architecture splits the system into a fast processor-memory bus and a slower peripheral bus connected by a bridge. The processor, cache, and memory run on the high-speed bus, while peripherals attach to the low-speed bus; the bridge translates protocols and isolates traffic, allowing the processor bus to operate at full speed.

Describe two-level bus architecture in detail.

In a two-level (hierarchical) bus architecture, the system uses two buses of different speed connected by a bridge, instead of one common bus.

 +-----------+      +--------+     +----------+
 | Processor |      | Cache/ |     |  Memory  |
 +-----+-----+      | DMA    |     +----+-----+
       |            +---+----+          |
 ======+================+===============+==== Processor-memory bus (fast)
                        |
                    +---+----+
                    | Bridge |
                    +---+----+
 =======================+====================== Peripheral bus (slow)
      |          |            |          |
   +--+--+    +--+--+      +--+--+    +--+--+
   |UART |    | Disk|      |Timer|    | I/O |
   +-----+    +-----+      +-----+    +-----+
  • Level 1: processor-local (processor-memory) bus: high speed, short, connects the processor, cache, memory and DMA.
  • Level 2: peripheral (I/O) bus: slower and standard (such as ISA/PCI), connecting peripherals.
  • Bridge: converts the protocols and speeds between the buses and isolates the high-speed bus from peripheral traffic.

Advantages: the processor and memory can run at full speed; peripheral traffic does not slow it; slow peripherals are cheap and standard, and different peripheral buses can be supported. Disadvantage: the bridge adds cost, delay and complexity.

✓ Answer checked by Claude Opus 5.5 (high effort)

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