Three-stage combination switch

Combination switch

A combination switch is a digital switch built by combining time (T) stages and space (S) stages. A pure time switch is limited by memory speed and a pure space switch cannot change time slots, so the two are combined to get a large switch that can change both the highway and the time slot of a sample. Examples: TS, ST (two-stage), TST, STS (three-stage), TSST, TSSST.

Three-stage combination switch (TST)

The most common three-stage combination switch is Time–Space–Time.

         Input T       Space S        Output T
 HW1 --->[TSI A1]--+-------------+--[TSI B1]---> HW1
 HW2 --->[TSI A2]--|  N x N TMS  |--[TSI B2]---> HW2
  ...      ...     |  (control   |    ...
 HWN --->[TSI AN]--|  memory)    |--[TSI BN]---> HWN
                   +-------------+
  c slots each      l internal slots    c slots

Block functions

• Input time stage: one TSI per incoming highway; moves a sample from its external slot to a chosen internal slot.
• Space stage: a time-multiplexed $N \times N$ space switch; in each internal slot it connects any input highway to any output highway.
• Output time stage: one TSI per outgoing highway; moves the sample from the internal slot to the required outgoing slot.
• Control unit: finds a free internal slot and writes all three control memories.

Working principle

Connect slot 4 of highway 1 (caller A) to slot 22 of highway N (called B):

1. The processor searches for an internal slot $x$ that is free at the output of TSI-A1 and at the input of TSI-BN, say $x = 10$.
2. Input T: TSI-A1 control memory set so the sample from slot 4 is read out in slot 10.
3. Space: control memory of column N set to "1" for slot 10; the crosspoint (1, N) closes in slot 10.
4. Output T: TSI-BN control memory set so the sample arriving in slot 10 is sent out in slot 22.
5. The B→A direction uses another internal slot, often $x + l/2$, so one search serves both directions.
6. On release, the control memory entries are cleared.

Blocking

There are $l$ alternative paths (internal slots). With link occupancy $p$ and $p' = pc/l$:

$$P_B = \left[1 - (1 - p')^2\right]^{l}$$

Non-blocking when $l \ge 2c - 1$.

Advantages: low blocking, cheap time expansion, small space stage, good for large exchanges. The other three-stage form, STS, uses space stages outside and TSIs in the middle, but needs more hardware for the same blocking.