K-map F(M,N,O,P) in SOP using NAND

Given $Y = F(M,N,O,P) = \Sigma m(0,1,2,8,12,14,15) + d(5,10,11)$, with M as the MSB.

K-map simplification

        OP
MN      00  01  11  10
      +---+---+---+---+
 00   | 1 | 1 | 0 | 1 |
      +---+---+---+---+
 01   | 0 | X | 0 | 0 |
      +---+---+---+---+
 11   | 1 | 0 | 1 | 1 |
      +---+---+---+---+
 10   | 1 | 0 | X | X |
      +---+---+---+---+

• Quad m(10,11,14,15) → $MO$
• Quad m(8,10,12,14) → $M\overline{P}$
• Quad m(0,2,8,10) → $\overline{N}\,\overline{P}$
• Pair m(0,1) → $\overline{M}\,\overline{N}\,\overline{O}$

SOP form

$$Y = MO + M\overline{P} + \overline{N}\,\overline{P} + \overline{M}\,\overline{N}\,\overline{O}$$

Check: 14, 15 by $MO$ (with 10, 11); 8, 12, 14 by $M\overline{P}$; 0, 2, 8 by $\overline{N}\,\overline{P}$ (with 10); 1 by $\overline{M}\,\overline{N}\,\overline{O}$. ($\overline{M}\,\overline{O}P$, cells 1 and 5, is an equally good choice for the last term.)

Realization using NAND gates only

An SOP expression maps directly to a two-level NAND-NAND circuit (De Morgan: $X + Y = \overline{\overline{X}\cdot\overline{Y}}$). Each product term becomes a first-level NAND and the output NAND replaces the OR gate. Complemented inputs are made with NAND gates whose inputs are tied.

$$Y = \overline{\overline{MO}\cdot\overline{M\overline{P}}\cdot\overline{\overline{N}\,\overline{P}}\cdot\overline{\overline{M}\,\overline{N}\,\overline{O}}}$$

M ──[NAND]── M'   (inputs tied)
N ──[NAND]── N'   (inputs tied)
O ──[NAND]── O'   (inputs tied)
P ──[NAND]── P'   (inputs tied)

M, O       ──[NAND]── G1  ─┐
M, P'      ──[NAND]── G2  ─┤
                           ├──[NAND]── Y
N', P'     ──[NAND]── G3  ─┤
M', N', O' ──[NAND]── G4  ─┘

Gates: 4 NAND inverters, 4 first-level NANDs and one 4-input output NAND.