TTL voltage profile; tristate TTL inverter

Voltage profile of TTL

The voltage profile of TTL ($V_{CC} = 5$ V) shows the voltage ranges that represent logic 0 and logic 1 at the output and at the input of a gate:

  Output (driving)       Input (receiving)
 5.0 +--------+         5.0 +--------+
     | HIGH   |             | HIGH   |
 2.4 +--------+ VOH(min) 2.0 +--------+ VIH(min)
     |invalid |  NM_H=0.4   | indet. |
 0.4 +--------+ VOL(max) 0.8 +--------+ VIL(max)
     | LOW    |  NM_L=0.4   | LOW    |
 0.0 +--------+         0.0 +--------+

• Output HIGH ≥ $V_{OH(min)} = 2.4$ V; output LOW ≤ $V_{OL(max)} = 0.4$ V.
• Input read as HIGH if ≥ $V_{IH(min)} = 2.0$ V; as LOW if ≤ $V_{IL(max)} = 0.8$ V; 0.8–2.0 V is indeterminate.
• Noise margins: $NM_H = 2.4 - 2.0 = 0.4$ V and $NM_L = 0.8 - 0.4 = 0.4$ V.

Tristate TTL inverter

A tristate (three-state) inverter has, besides the normal HIGH and LOW outputs, a third high-impedance (Hi-Z) state in which the output is effectively disconnected. It is used to connect many outputs to a common bus, with only one enabled at a time.

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
E--e     c--+  c     |    e
   |        +--b Q2  |   D1
   |           e     |    |
   |           +--+  |    +---- Y
   |           |  |  |    c
   |        R3 1k +--)--b Q4
   |           |     |    e
   |          GND   D2    |
   |                 |   GND
   +----- E line ----+

Q1 has a second emitter tied to the enable line E; diode D2 has its anode at Q3's base (Q2 collector) and its cathode on E.

Working:

• E = 1 (enabled): the second emitter of Q1 and diode D2 are reverse biased and have no effect. The circuit works as a normal TTL inverter: A = 0 → Q2, Q4 OFF, Q3 ON → Y = 1; A = 1 → Q2, Q4 ON, Q3 OFF → Y = 0.
• E = 0 (disabled): the E emitter of Q1 conducts, so Q2 and Q4 are OFF whatever A is. D2 also conducts and clamps Q3's base to about 0.9 V, which is not enough for Q3 and D1, so Q3 is OFF too. With both totem-pole transistors OFF the output floats: Hi-Z.

In ICs such as the 74125/74126 buffers the external enable pin may be active-LOW, with an internal inverter driving this E line.