TTL inverter schematic and working

A TTL inverter (7404) is the TTL NAND circuit with a single-emitter input transistor.

Schematic diagram

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
         c--+  c          e
            +--b Q2       |
               e         D1
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

• Q1: input transistor (base through R1 = 4 kΩ to $V_{CC}$).
• Q2: phase splitter (R2 = 1.6 kΩ collector, R3 = 1 kΩ emitter).
• Q3, D1, Q4: totem-pole output (R4 = 130 Ω).

Working principle

• A = 0 (≈ 0.2 V): Q1's base–emitter junction is forward biased; its base is at about 0.2 + 0.7 = 0.9 V. Turning on Q2 and Q4 needs about 2.1 V at Q1's base (Q1's base–collector junction plus the base–emitter junctions of Q2 and Q4), so Q2 and Q4 stay OFF. Q2's collector is pulled up by R2, so Q3 is ON (emitter follower) and current flows from $V_{CC}$ through R4, Q3 and D1 to the load. Output Y ≈ 3.4 V (HIGH).
• A = 1 (≥ 2.0 V): Q1's emitter junction is reverse biased; R1 current flows through Q1's base–collector junction into Q2's base, and Q1's base rises to about 2.1 V. Q2 saturates, its emitter current through R3 drives Q4 into saturation, and the output is pulled to $V_{CE(sat)} \approx 0.2$ V (LOW). Q2's collector is at about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1 (needs about 1.4 V above the 0.2 V output), so Q3 is OFF.

So $Y = \overline{A}$. The totem pole gives low output resistance in both states, so the gate switches quickly (≈ 10 ns) and can drive 10 standard TTL loads.